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FFmpeg/libavcodec/sparc/vis.h

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  1. /*

  2.  * vis.h

  3.  * Copyright (C) 2003 David S. Miller <davem@redhat.com>

  4.  *

  5.  * This file is part of FFmpeg.

  6.  *

  7.  * FFmpeg is free software; you can redistribute it and/or

  8.  * modify it under the terms of the GNU Lesser General Public

  9.  * License as published by the Free Software Foundation; either

  10.  * version 2.1 of the License, or (at your option) any later version.

  11.  *

  12.  * FFmpeg is distributed in the hope that it will be useful,

  13.  * but WITHOUT ANY WARRANTY; without even the implied warranty of

  14.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

  15.  * Lesser General Public License for more details.

  16.  *

  17.  * You should have received a copy of the GNU Lesser General Public

  18.  * License along with FFmpeg; if not, write to the Free Software

  19.  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA

  20.  */

  21. 

  22. /* You may be asking why I hard-code the instruction opcodes and don't

  23.  * use the normal VIS assembler mnenomics for the VIS instructions.

  24.  *

  25.  * The reason is that Sun, in their infinite wisdom, decided that a binary

  26.  * using a VIS instruction will cause it to be marked (in the ELF headers)

  27.  * as doing so, and this prevents the OS from loading such binaries if the

  28.  * current cpu doesn't have VIS.  There is no way to easily override this

  29.  * behavior of the assembler that I am aware of.

  30.  *

  31.  * This totally defeats what libmpeg2 is trying to do which is allow a

  32.  * single binary to be created, and then detect the availability of VIS

  33.  * at runtime.

  34.  *

  35.  * I'm not saying that tainting the binary by default is bad, rather I'm

  36.  * saying that not providing a way to override this easily unnecessarily

  37.  * ties people's hands.

  38.  *

  39.  * Thus, we do the opcode encoding by hand and output 32-bit words in

  40.  * the assembler to keep the binary from becoming tainted.

  41.  */

  42. 

  43. #define vis_opc_base    ((0x1 << 31) | (0x36 << 19))

  44. #define vis_opf(X)      ((X) << 5)

  45. #define vis_sreg(X)     (X)

  46. #define vis_dreg(X)     (((X)&0x1f)|((X)>>5))

  47. #define vis_rs1_s(X)    (vis_sreg(X) << 14)

  48. #define vis_rs1_d(X)    (vis_dreg(X) << 14)

  49. #define vis_rs2_s(X)    (vis_sreg(X) << 0)

  50. #define vis_rs2_d(X)    (vis_dreg(X) << 0)

  51. #define vis_rd_s(X)     (vis_sreg(X) << 25)

  52. #define vis_rd_d(X)     (vis_dreg(X) << 25)

  53. 

  54. #define vis_ss2s(opf,rs1,rs2,rd) \

  55.         __asm__ __volatile__ (".word %0" \

  56.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  57.                                        vis_rs1_s(rs1) | \

  58.                                        vis_rs2_s(rs2) | \

  59.                                        vis_rd_s(rd)))

  60. 

  61. #define vis_dd2d(opf,rs1,rs2,rd) \

  62.         __asm__ __volatile__ (".word %0" \

  63.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  64.                                        vis_rs1_d(rs1) | \

  65.                                        vis_rs2_d(rs2) | \

  66.                                        vis_rd_d(rd)))

  67. 

  68. #define vis_ss2d(opf,rs1,rs2,rd) \

  69.         __asm__ __volatile__ (".word %0" \

  70.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  71.                                        vis_rs1_s(rs1) | \

  72.                                        vis_rs2_s(rs2) | \

  73.                                        vis_rd_d(rd)))

  74. 

  75. #define vis_sd2d(opf,rs1,rs2,rd) \

  76.         __asm__ __volatile__ (".word %0" \

  77.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  78.                                        vis_rs1_s(rs1) | \

  79.                                        vis_rs2_d(rs2) | \

  80.                                        vis_rd_d(rd)))

  81. 

  82. #define vis_d2s(opf,rs2,rd) \

  83.         __asm__ __volatile__ (".word %0" \

  84.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  85.                                        vis_rs2_d(rs2) | \

  86.                                        vis_rd_s(rd)))

  87. 

  88. #define vis_s2d(opf,rs2,rd) \

  89.         __asm__ __volatile__ (".word %0" \

  90.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  91.                                        vis_rs2_s(rs2) | \

  92.                                        vis_rd_d(rd)))

  93. 

  94. #define vis_d12d(opf,rs1,rd) \

  95.         __asm__ __volatile__ (".word %0" \

  96.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  97.                                        vis_rs1_d(rs1) | \

  98.                                        vis_rd_d(rd)))

  99. 

  100. #define vis_d22d(opf,rs2,rd) \

  101.         __asm__ __volatile__ (".word %0" \

  102.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  103.                                        vis_rs2_d(rs2) | \

  104.                                        vis_rd_d(rd)))

  105. 

  106. #define vis_s12s(opf,rs1,rd) \

  107.         __asm__ __volatile__ (".word %0" \

  108.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  109.                                        vis_rs1_s(rs1) | \

  110.                                        vis_rd_s(rd)))

  111. 

  112. #define vis_s22s(opf,rs2,rd) \

  113.         __asm__ __volatile__ (".word %0" \

  114.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  115.                                        vis_rs2_s(rs2) | \

  116.                                        vis_rd_s(rd)))

  117. 

  118. #define vis_s(opf,rd) \

  119.         __asm__ __volatile__ (".word %0" \

  120.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  121.                                        vis_rd_s(rd)))

  122. 

  123. #define vis_d(opf,rd) \

  124.         __asm__ __volatile__ (".word %0" \

  125.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  126.                                        vis_rd_d(rd)))

  127. 

  128. #define vis_r2m(op,rd,mem) \

  129.         __asm__ __volatile__ (#op "\t%%f" #rd ", [%0]" : : "r" (&(mem)) )

  130. 

  131. #define vis_r2m_2(op,rd,mem1,mem2) \

  132.         __asm__ __volatile__ (#op "\t%%f" #rd ", [%0 + %1]" : : "r" (mem1), "r" (mem2) )

  133. 

  134. #define vis_m2r(op,mem,rd) \

  135.         __asm__ __volatile__ (#op "\t[%0], %%f" #rd : : "r" (&(mem)) )

  136. 

  137. #define vis_m2r_2(op,mem1,mem2,rd) \

  138.         __asm__ __volatile__ (#op "\t[%0 + %1], %%f" #rd : : "r" (mem1), "r" (mem2) )

  139. 

  140. static inline void vis_set_gsr(unsigned int _val)

  141. {

  142.         register unsigned int val asm("g1");

  143. 

  144.         val = _val;

  145.         __asm__ __volatile__(".word 0xa7804000"

  146.                              : : "r" (val));

  147. }

  148. 

  149. #define VIS_GSR_ALIGNADDR_MASK          0x0000007

  150. #define VIS_GSR_ALIGNADDR_SHIFT         0

  151. #define VIS_GSR_SCALEFACT_MASK          0x0000078

  152. #define VIS_GSR_SCALEFACT_SHIFT         3

  153. 

  154. #define vis_ld32(mem,rs1)               vis_m2r(ld, mem, rs1)

  155. #define vis_ld32_2(mem1,mem2,rs1)       vis_m2r_2(ld, mem1, mem2, rs1)

  156. #define vis_st32(rs1,mem)               vis_r2m(st, rs1, mem)

  157. #define vis_st32_2(rs1,mem1,mem2)       vis_r2m_2(st, rs1, mem1, mem2)

  158. #define vis_ld64(mem,rs1)               vis_m2r(ldd, mem, rs1)

  159. #define vis_ld64_2(mem1,mem2,rs1)       vis_m2r_2(ldd, mem1, mem2, rs1)

  160. #define vis_st64(rs1,mem)               vis_r2m(std, rs1, mem)

  161. #define vis_st64_2(rs1,mem1,mem2)       vis_r2m_2(std, rs1, mem1, mem2)

  162. 

  163. #define vis_ldblk(mem, rd) \

  164. do {        register void *__mem asm("g1"); \

  165.         __mem = &(mem); \

  166.         __asm__ __volatile__(".word 0xc1985e00 | %1" \

  167.                              : \

  168.                              : "r" (__mem), \

  169.                                "i" (vis_rd_d(rd)) \

  170.                              : "memory"); \

  171. } while (0)

  172. 

  173. #define vis_stblk(rd, mem) \

  174. do {        register void *__mem asm("g1"); \

  175.         __mem = &(mem); \

  176.         __asm__ __volatile__(".word 0xc1b85e00 | %1" \

  177.                              : \

  178.                              : "r" (__mem), \

  179.                                "i" (vis_rd_d(rd)) \

  180.                              : "memory"); \

  181. } while (0)

  182. 

  183. #define vis_membar_storestore()        \

  184.         __asm__ __volatile__(".word 0x8143e008" : : : "memory")

  185. 

  186. #define vis_membar_sync()        \

  187.         __asm__ __volatile__(".word 0x8143e040" : : : "memory")

  188. 

  189. /* 16 and 32 bit partitioned addition and subtraction.  The normal

  190.  * versions perform 4 16-bit or 2 32-bit additions or subtractions.

  191.  * The 's' versions perform 2 16-bit or 1 32-bit additions or

  192.  * subtractions.

  193.  */

  194. 

  195. #define vis_padd16(rs1,rs2,rd)          vis_dd2d(0x50, rs1, rs2, rd)

  196. #define vis_padd16s(rs1,rs2,rd)         vis_ss2s(0x51, rs1, rs2, rd)

  197. #define vis_padd32(rs1,rs2,rd)          vis_dd2d(0x52, rs1, rs2, rd)

  198. #define vis_padd32s(rs1,rs2,rd)         vis_ss2s(0x53, rs1, rs2, rd)

  199. #define vis_psub16(rs1,rs2,rd)          vis_dd2d(0x54, rs1, rs2, rd)

  200. #define vis_psub16s(rs1,rs2,rd)         vis_ss2s(0x55, rs1, rs2, rd)

  201. #define vis_psub32(rs1,rs2,rd)          vis_dd2d(0x56, rs1, rs2, rd)

  202. #define vis_psub32s(rs1,rs2,rd)         vis_ss2s(0x57, rs1, rs2, rd)

  203. 

  204. /* Pixel formatting instructions.  */

  205. 

  206. #define vis_pack16(rs2,rd)              vis_d2s( 0x3b,      rs2, rd)

  207. #define vis_pack32(rs1,rs2,rd)          vis_dd2d(0x3a, rs1, rs2, rd)

  208. #define vis_packfix(rs2,rd)             vis_d2s( 0x3d,      rs2, rd)

  209. #define vis_expand(rs2,rd)              vis_s2d( 0x4d,      rs2, rd)

  210. #define vis_pmerge(rs1,rs2,rd)          vis_ss2d(0x4b, rs1, rs2, rd)

  211. 

  212. /* Partitioned multiply instructions.  */

  213. 

  214. #define vis_mul8x16(rs1,rs2,rd)         vis_sd2d(0x31, rs1, rs2, rd)

  215. #define vis_mul8x16au(rs1,rs2,rd)       vis_ss2d(0x33, rs1, rs2, rd)

  216. #define vis_mul8x16al(rs1,rs2,rd)       vis_ss2d(0x35, rs1, rs2, rd)

  217. #define vis_mul8sux16(rs1,rs2,rd)       vis_dd2d(0x36, rs1, rs2, rd)

  218. #define vis_mul8ulx16(rs1,rs2,rd)       vis_dd2d(0x37, rs1, rs2, rd)

  219. #define vis_muld8sux16(rs1,rs2,rd)      vis_ss2d(0x38, rs1, rs2, rd)

  220. #define vis_muld8ulx16(rs1,rs2,rd)      vis_ss2d(0x39, rs1, rs2, rd)

  221. 

  222. /* Alignment instructions.  */

  223. 

  224. static inline void *vis_alignaddr(void *_ptr)

  225. {

  226.         register void *ptr asm("g1");

  227. 

  228.         ptr = _ptr;

  229. 

  230.         __asm__ __volatile__(".word %2"

  231.                              : "=&r" (ptr)

  232.                              : "0" (ptr),

  233.                                "i" (vis_opc_base | vis_opf(0x18) |

  234.                                     vis_rs1_s(1) |

  235.                                     vis_rs2_s(0) |

  236.                                     vis_rd_s(1)));

  237. 

  238.         return ptr;

  239. }

  240. 

  241. static inline void vis_alignaddr_g0(void *_ptr)

  242. {

  243.         register void *ptr asm("g1");

  244. 

  245.         ptr = _ptr;

  246. 

  247.         __asm__ __volatile__(".word %2"

  248.                              : "=&r" (ptr)

  249.                              : "0" (ptr),

  250.                                "i" (vis_opc_base | vis_opf(0x18) |

  251.                                     vis_rs1_s(1) |

  252.                                     vis_rs2_s(0) |

  253.                                     vis_rd_s(0)));

  254. }

  255. 

  256. static inline void *vis_alignaddrl(void *_ptr)

  257. {

  258.         register void *ptr asm("g1");

  259. 

  260.         ptr = _ptr;

  261. 

  262.         __asm__ __volatile__(".word %2"

  263.                              : "=&r" (ptr)

  264.                              : "0" (ptr),

  265.                                "i" (vis_opc_base | vis_opf(0x19) |

  266.                                     vis_rs1_s(1) |

  267.                                     vis_rs2_s(0) |

  268.                                     vis_rd_s(1)));

  269. 

  270.         return ptr;

  271. }

  272. 

  273. static inline void vis_alignaddrl_g0(void *_ptr)

  274. {

  275.         register void *ptr asm("g1");

  276. 

  277.         ptr = _ptr;

  278. 

  279.         __asm__ __volatile__(".word %2"

  280.                              : "=&r" (ptr)

  281.                              : "0" (ptr),

  282.                                "i" (vis_opc_base | vis_opf(0x19) |

  283.                                     vis_rs1_s(1) |

  284.                                     vis_rs2_s(0) |

  285.                                     vis_rd_s(0)));

  286. }

  287. 

  288. #define vis_faligndata(rs1,rs2,rd)        vis_dd2d(0x48, rs1, rs2, rd)

  289. 

  290. /* Logical operate instructions.  */

  291. 

  292. #define vis_fzero(rd)                   vis_d(   0x60,           rd)

  293. #define vis_fzeros(rd)                  vis_s(   0x61,           rd)

  294. #define vis_fone(rd)                    vis_d(   0x7e,           rd)

  295. #define vis_fones(rd)                   vis_s(   0x7f,           rd)

  296. #define vis_src1(rs1,rd)                vis_d12d(0x74, rs1,      rd)

  297. #define vis_src1s(rs1,rd)               vis_s12s(0x75, rs1,      rd)

  298. #define vis_src2(rs2,rd)                vis_d22d(0x78,      rs2, rd)

  299. #define vis_src2s(rs2,rd)               vis_s22s(0x79,      rs2, rd)

  300. #define vis_not1(rs1,rd)                vis_d12d(0x6a, rs1,      rd)

  301. #define vis_not1s(rs1,rd)               vis_s12s(0x6b, rs1,      rd)

  302. #define vis_not2(rs2,rd)                vis_d22d(0x66,      rs2, rd)

  303. #define vis_not2s(rs2,rd)               vis_s22s(0x67,      rs2, rd)

  304. #define vis_or(rs1,rs2,rd)              vis_dd2d(0x7c, rs1, rs2, rd)

  305. #define vis_ors(rs1,rs2,rd)             vis_ss2s(0x7d, rs1, rs2, rd)

  306. #define vis_nor(rs1,rs2,rd)             vis_dd2d(0x62, rs1, rs2, rd)

  307. #define vis_nors(rs1,rs2,rd)            vis_ss2s(0x63, rs1, rs2, rd)

  308. #define vis_and(rs1,rs2,rd)             vis_dd2d(0x70, rs1, rs2, rd)

  309. #define vis_ands(rs1,rs2,rd)            vis_ss2s(0x71, rs1, rs2, rd)

  310. #define vis_nand(rs1,rs2,rd)            vis_dd2d(0x6e, rs1, rs2, rd)

  311. #define vis_nands(rs1,rs2,rd)           vis_ss2s(0x6f, rs1, rs2, rd)

  312. #define vis_xor(rs1,rs2,rd)             vis_dd2d(0x6c, rs1, rs2, rd)

  313. #define vis_xors(rs1,rs2,rd)            vis_ss2s(0x6d, rs1, rs2, rd)

  314. #define vis_xnor(rs1,rs2,rd)            vis_dd2d(0x72, rs1, rs2, rd)

  315. #define vis_xnors(rs1,rs2,rd)           vis_ss2s(0x73, rs1, rs2, rd)

  316. #define vis_ornot1(rs1,rs2,rd)          vis_dd2d(0x7a, rs1, rs2, rd)

  317. #define vis_ornot1s(rs1,rs2,rd)         vis_ss2s(0x7b, rs1, rs2, rd)

  318. #define vis_ornot2(rs1,rs2,rd)          vis_dd2d(0x76, rs1, rs2, rd)

  319. #define vis_ornot2s(rs1,rs2,rd)         vis_ss2s(0x77, rs1, rs2, rd)

  320. #define vis_andnot1(rs1,rs2,rd)         vis_dd2d(0x68, rs1, rs2, rd)

  321. #define vis_andnot1s(rs1,rs2,rd)        vis_ss2s(0x69, rs1, rs2, rd)

  322. #define vis_andnot2(rs1,rs2,rd)         vis_dd2d(0x64, rs1, rs2, rd)

  323. #define vis_andnot2s(rs1,rs2,rd)        vis_ss2s(0x65, rs1, rs2, rd)

  324. 

  325. /* Pixel component distance.  */

  326. 

  327. #define vis_pdist(rs1,rs2,rd)           vis_dd2d(0x3e, rs1, rs2, rd)