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  1. /*
  2. * VC-1 and WMV3 - DSP functions MMX-optimized
  3. * Copyright (c) 2007 Christophe GISQUET <christophe.gisquet@free.fr>
  4. *
  5. * Permission is hereby granted, free of charge, to any person
  6. * obtaining a copy of this software and associated documentation
  7. * files (the "Software"), to deal in the Software without
  8. * restriction, including without limitation the rights to use,
  9. * copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following
  12. * conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be
  15. * included in all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  19. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  20. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  21. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  22. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  23. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  24. * OTHER DEALINGS IN THE SOFTWARE.
  25. */
  26. #include "libavutil/cpu.h"
  27. #include "libavutil/internal.h"
  28. #include "libavutil/mem.h"
  29. #include "libavutil/x86/asm.h"
  30. #include "libavutil/x86/cpu.h"
  31. #include "dsputil_mmx.h"
  32. #include "libavcodec/vc1dsp.h"
  33. #include "vc1dsp.h"
  34. #if HAVE_INLINE_ASM
  35. #define OP_PUT(S,D)
  36. #define OP_AVG(S,D) "pavgb " #S ", " #D " \n\t"
  37. /** Add rounder from mm7 to mm3 and pack result at destination */
  38. #define NORMALIZE_MMX(SHIFT) \
  39. "paddw %%mm7, %%mm3 \n\t" /* +bias-r */ \
  40. "paddw %%mm7, %%mm4 \n\t" /* +bias-r */ \
  41. "psraw "SHIFT", %%mm3 \n\t" \
  42. "psraw "SHIFT", %%mm4 \n\t"
  43. #define TRANSFER_DO_PACK(OP) \
  44. "packuswb %%mm4, %%mm3 \n\t" \
  45. OP((%2), %%mm3) \
  46. "movq %%mm3, (%2) \n\t"
  47. #define TRANSFER_DONT_PACK(OP) \
  48. OP(0(%2), %%mm3) \
  49. OP(8(%2), %%mm4) \
  50. "movq %%mm3, 0(%2) \n\t" \
  51. "movq %%mm4, 8(%2) \n\t"
  52. /** @see MSPEL_FILTER13_CORE for use as UNPACK macro */
  53. #define DO_UNPACK(reg) "punpcklbw %%mm0, " reg "\n\t"
  54. #define DONT_UNPACK(reg)
  55. /** Compute the rounder 32-r or 8-r and unpacks it to mm7 */
  56. #define LOAD_ROUNDER_MMX(ROUND) \
  57. "movd "ROUND", %%mm7 \n\t" \
  58. "punpcklwd %%mm7, %%mm7 \n\t" \
  59. "punpckldq %%mm7, %%mm7 \n\t"
  60. #define SHIFT2_LINE(OFF, R0,R1,R2,R3) \
  61. "paddw %%mm"#R2", %%mm"#R1" \n\t" \
  62. "movd (%0,%3), %%mm"#R0" \n\t" \
  63. "pmullw %%mm6, %%mm"#R1" \n\t" \
  64. "punpcklbw %%mm0, %%mm"#R0" \n\t" \
  65. "movd (%0,%2), %%mm"#R3" \n\t" \
  66. "psubw %%mm"#R0", %%mm"#R1" \n\t" \
  67. "punpcklbw %%mm0, %%mm"#R3" \n\t" \
  68. "paddw %%mm7, %%mm"#R1" \n\t" \
  69. "psubw %%mm"#R3", %%mm"#R1" \n\t" \
  70. "psraw %4, %%mm"#R1" \n\t" \
  71. "movq %%mm"#R1", "#OFF"(%1) \n\t" \
  72. "add %2, %0 \n\t"
  73. /** Sacrifying mm6 allows to pipeline loads from src */
  74. static void vc1_put_ver_16b_shift2_mmx(int16_t *dst,
  75. const uint8_t *src, x86_reg stride,
  76. int rnd, int64_t shift)
  77. {
  78. __asm__ volatile(
  79. "mov $3, %%"REG_c" \n\t"
  80. LOAD_ROUNDER_MMX("%5")
  81. "movq "MANGLE(ff_pw_9)", %%mm6 \n\t"
  82. "1: \n\t"
  83. "movd (%0), %%mm2 \n\t"
  84. "add %2, %0 \n\t"
  85. "movd (%0), %%mm3 \n\t"
  86. "punpcklbw %%mm0, %%mm2 \n\t"
  87. "punpcklbw %%mm0, %%mm3 \n\t"
  88. SHIFT2_LINE( 0, 1, 2, 3, 4)
  89. SHIFT2_LINE( 24, 2, 3, 4, 1)
  90. SHIFT2_LINE( 48, 3, 4, 1, 2)
  91. SHIFT2_LINE( 72, 4, 1, 2, 3)
  92. SHIFT2_LINE( 96, 1, 2, 3, 4)
  93. SHIFT2_LINE(120, 2, 3, 4, 1)
  94. SHIFT2_LINE(144, 3, 4, 1, 2)
  95. SHIFT2_LINE(168, 4, 1, 2, 3)
  96. "sub %6, %0 \n\t"
  97. "add $8, %1 \n\t"
  98. "dec %%"REG_c" \n\t"
  99. "jnz 1b \n\t"
  100. : "+r"(src), "+r"(dst)
  101. : "r"(stride), "r"(-2*stride),
  102. "m"(shift), "m"(rnd), "r"(9*stride-4)
  103. : "%"REG_c, "memory"
  104. );
  105. }
  106. /**
  107. * Data is already unpacked, so some operations can directly be made from
  108. * memory.
  109. */
  110. #define VC1_HOR_16b_SHIFT2(OP, OPNAME)\
  111. static void OPNAME ## vc1_hor_16b_shift2_mmx(uint8_t *dst, x86_reg stride,\
  112. const int16_t *src, int rnd)\
  113. {\
  114. int h = 8;\
  115. \
  116. src -= 1;\
  117. rnd -= (-1+9+9-1)*1024; /* Add -1024 bias */\
  118. __asm__ volatile(\
  119. LOAD_ROUNDER_MMX("%4")\
  120. "movq "MANGLE(ff_pw_128)", %%mm6\n\t"\
  121. "movq "MANGLE(ff_pw_9)", %%mm5 \n\t"\
  122. "1: \n\t"\
  123. "movq 2*0+0(%1), %%mm1 \n\t"\
  124. "movq 2*0+8(%1), %%mm2 \n\t"\
  125. "movq 2*1+0(%1), %%mm3 \n\t"\
  126. "movq 2*1+8(%1), %%mm4 \n\t"\
  127. "paddw 2*3+0(%1), %%mm1 \n\t"\
  128. "paddw 2*3+8(%1), %%mm2 \n\t"\
  129. "paddw 2*2+0(%1), %%mm3 \n\t"\
  130. "paddw 2*2+8(%1), %%mm4 \n\t"\
  131. "pmullw %%mm5, %%mm3 \n\t"\
  132. "pmullw %%mm5, %%mm4 \n\t"\
  133. "psubw %%mm1, %%mm3 \n\t"\
  134. "psubw %%mm2, %%mm4 \n\t"\
  135. NORMALIZE_MMX("$7")\
  136. /* Remove bias */\
  137. "paddw %%mm6, %%mm3 \n\t"\
  138. "paddw %%mm6, %%mm4 \n\t"\
  139. TRANSFER_DO_PACK(OP)\
  140. "add $24, %1 \n\t"\
  141. "add %3, %2 \n\t"\
  142. "decl %0 \n\t"\
  143. "jnz 1b \n\t"\
  144. : "+r"(h), "+r" (src), "+r" (dst)\
  145. : "r"(stride), "m"(rnd)\
  146. : "memory"\
  147. );\
  148. }
  149. VC1_HOR_16b_SHIFT2(OP_PUT, put_)
  150. VC1_HOR_16b_SHIFT2(OP_AVG, avg_)
  151. /**
  152. * Purely vertical or horizontal 1/2 shift interpolation.
  153. * Sacrify mm6 for *9 factor.
  154. */
  155. #define VC1_SHIFT2(OP, OPNAME)\
  156. static void OPNAME ## vc1_shift2_mmx(uint8_t *dst, const uint8_t *src,\
  157. x86_reg stride, int rnd, x86_reg offset)\
  158. {\
  159. rnd = 8-rnd;\
  160. __asm__ volatile(\
  161. "mov $8, %%"REG_c" \n\t"\
  162. LOAD_ROUNDER_MMX("%5")\
  163. "movq "MANGLE(ff_pw_9)", %%mm6\n\t"\
  164. "1: \n\t"\
  165. "movd 0(%0 ), %%mm3 \n\t"\
  166. "movd 4(%0 ), %%mm4 \n\t"\
  167. "movd 0(%0,%2), %%mm1 \n\t"\
  168. "movd 4(%0,%2), %%mm2 \n\t"\
  169. "add %2, %0 \n\t"\
  170. "punpcklbw %%mm0, %%mm3 \n\t"\
  171. "punpcklbw %%mm0, %%mm4 \n\t"\
  172. "punpcklbw %%mm0, %%mm1 \n\t"\
  173. "punpcklbw %%mm0, %%mm2 \n\t"\
  174. "paddw %%mm1, %%mm3 \n\t"\
  175. "paddw %%mm2, %%mm4 \n\t"\
  176. "movd 0(%0,%3), %%mm1 \n\t"\
  177. "movd 4(%0,%3), %%mm2 \n\t"\
  178. "pmullw %%mm6, %%mm3 \n\t" /* 0,9,9,0*/\
  179. "pmullw %%mm6, %%mm4 \n\t" /* 0,9,9,0*/\
  180. "punpcklbw %%mm0, %%mm1 \n\t"\
  181. "punpcklbw %%mm0, %%mm2 \n\t"\
  182. "psubw %%mm1, %%mm3 \n\t" /*-1,9,9,0*/\
  183. "psubw %%mm2, %%mm4 \n\t" /*-1,9,9,0*/\
  184. "movd 0(%0,%2), %%mm1 \n\t"\
  185. "movd 4(%0,%2), %%mm2 \n\t"\
  186. "punpcklbw %%mm0, %%mm1 \n\t"\
  187. "punpcklbw %%mm0, %%mm2 \n\t"\
  188. "psubw %%mm1, %%mm3 \n\t" /*-1,9,9,-1*/\
  189. "psubw %%mm2, %%mm4 \n\t" /*-1,9,9,-1*/\
  190. NORMALIZE_MMX("$4")\
  191. "packuswb %%mm4, %%mm3 \n\t"\
  192. OP((%1), %%mm3)\
  193. "movq %%mm3, (%1) \n\t"\
  194. "add %6, %0 \n\t"\
  195. "add %4, %1 \n\t"\
  196. "dec %%"REG_c" \n\t"\
  197. "jnz 1b \n\t"\
  198. : "+r"(src), "+r"(dst)\
  199. : "r"(offset), "r"(-2*offset), "g"(stride), "m"(rnd),\
  200. "g"(stride-offset)\
  201. : "%"REG_c, "memory"\
  202. );\
  203. }
  204. VC1_SHIFT2(OP_PUT, put_)
  205. VC1_SHIFT2(OP_AVG, avg_)
  206. /**
  207. * Core of the 1/4 and 3/4 shift bicubic interpolation.
  208. *
  209. * @param UNPACK Macro unpacking arguments from 8 to 16bits (can be empty).
  210. * @param MOVQ "movd 1" or "movq 2", if data read is already unpacked.
  211. * @param A1 Address of 1st tap (beware of unpacked/packed).
  212. * @param A2 Address of 2nd tap
  213. * @param A3 Address of 3rd tap
  214. * @param A4 Address of 4th tap
  215. */
  216. #define MSPEL_FILTER13_CORE(UNPACK, MOVQ, A1, A2, A3, A4) \
  217. MOVQ "*0+"A1", %%mm1 \n\t" \
  218. MOVQ "*4+"A1", %%mm2 \n\t" \
  219. UNPACK("%%mm1") \
  220. UNPACK("%%mm2") \
  221. "pmullw "MANGLE(ff_pw_3)", %%mm1\n\t" \
  222. "pmullw "MANGLE(ff_pw_3)", %%mm2\n\t" \
  223. MOVQ "*0+"A2", %%mm3 \n\t" \
  224. MOVQ "*4+"A2", %%mm4 \n\t" \
  225. UNPACK("%%mm3") \
  226. UNPACK("%%mm4") \
  227. "pmullw %%mm6, %%mm3 \n\t" /* *18 */ \
  228. "pmullw %%mm6, %%mm4 \n\t" /* *18 */ \
  229. "psubw %%mm1, %%mm3 \n\t" /* 18,-3 */ \
  230. "psubw %%mm2, %%mm4 \n\t" /* 18,-3 */ \
  231. MOVQ "*0+"A4", %%mm1 \n\t" \
  232. MOVQ "*4+"A4", %%mm2 \n\t" \
  233. UNPACK("%%mm1") \
  234. UNPACK("%%mm2") \
  235. "psllw $2, %%mm1 \n\t" /* 4* */ \
  236. "psllw $2, %%mm2 \n\t" /* 4* */ \
  237. "psubw %%mm1, %%mm3 \n\t" /* -4,18,-3 */ \
  238. "psubw %%mm2, %%mm4 \n\t" /* -4,18,-3 */ \
  239. MOVQ "*0+"A3", %%mm1 \n\t" \
  240. MOVQ "*4+"A3", %%mm2 \n\t" \
  241. UNPACK("%%mm1") \
  242. UNPACK("%%mm2") \
  243. "pmullw %%mm5, %%mm1 \n\t" /* *53 */ \
  244. "pmullw %%mm5, %%mm2 \n\t" /* *53 */ \
  245. "paddw %%mm1, %%mm3 \n\t" /* 4,53,18,-3 */ \
  246. "paddw %%mm2, %%mm4 \n\t" /* 4,53,18,-3 */
  247. /**
  248. * Macro to build the vertical 16bits version of vc1_put_shift[13].
  249. * Here, offset=src_stride. Parameters passed A1 to A4 must use
  250. * %3 (src_stride) and %4 (3*src_stride).
  251. *
  252. * @param NAME Either 1 or 3
  253. * @see MSPEL_FILTER13_CORE for information on A1->A4
  254. */
  255. #define MSPEL_FILTER13_VER_16B(NAME, A1, A2, A3, A4) \
  256. static void \
  257. vc1_put_ver_16b_ ## NAME ## _mmx(int16_t *dst, const uint8_t *src, \
  258. x86_reg src_stride, \
  259. int rnd, int64_t shift) \
  260. { \
  261. int h = 8; \
  262. src -= src_stride; \
  263. __asm__ volatile( \
  264. LOAD_ROUNDER_MMX("%5") \
  265. "movq "MANGLE(ff_pw_53)", %%mm5\n\t" \
  266. "movq "MANGLE(ff_pw_18)", %%mm6\n\t" \
  267. ".p2align 3 \n\t" \
  268. "1: \n\t" \
  269. MSPEL_FILTER13_CORE(DO_UNPACK, "movd 1", A1, A2, A3, A4) \
  270. NORMALIZE_MMX("%6") \
  271. TRANSFER_DONT_PACK(OP_PUT) \
  272. /* Last 3 (in fact 4) bytes on the line */ \
  273. "movd 8+"A1", %%mm1 \n\t" \
  274. DO_UNPACK("%%mm1") \
  275. "movq %%mm1, %%mm3 \n\t" \
  276. "paddw %%mm1, %%mm1 \n\t" \
  277. "paddw %%mm3, %%mm1 \n\t" /* 3* */ \
  278. "movd 8+"A2", %%mm3 \n\t" \
  279. DO_UNPACK("%%mm3") \
  280. "pmullw %%mm6, %%mm3 \n\t" /* *18 */ \
  281. "psubw %%mm1, %%mm3 \n\t" /*18,-3 */ \
  282. "movd 8+"A3", %%mm1 \n\t" \
  283. DO_UNPACK("%%mm1") \
  284. "pmullw %%mm5, %%mm1 \n\t" /* *53 */ \
  285. "paddw %%mm1, %%mm3 \n\t" /*53,18,-3 */ \
  286. "movd 8+"A4", %%mm1 \n\t" \
  287. DO_UNPACK("%%mm1") \
  288. "psllw $2, %%mm1 \n\t" /* 4* */ \
  289. "psubw %%mm1, %%mm3 \n\t" \
  290. "paddw %%mm7, %%mm3 \n\t" \
  291. "psraw %6, %%mm3 \n\t" \
  292. "movq %%mm3, 16(%2) \n\t" \
  293. "add %3, %1 \n\t" \
  294. "add $24, %2 \n\t" \
  295. "decl %0 \n\t" \
  296. "jnz 1b \n\t" \
  297. : "+r"(h), "+r" (src), "+r" (dst) \
  298. : "r"(src_stride), "r"(3*src_stride), \
  299. "m"(rnd), "m"(shift) \
  300. : "memory" \
  301. ); \
  302. }
  303. /**
  304. * Macro to build the horizontal 16bits version of vc1_put_shift[13].
  305. * Here, offset=16bits, so parameters passed A1 to A4 should be simple.
  306. *
  307. * @param NAME Either 1 or 3
  308. * @see MSPEL_FILTER13_CORE for information on A1->A4
  309. */
  310. #define MSPEL_FILTER13_HOR_16B(NAME, A1, A2, A3, A4, OP, OPNAME) \
  311. static void \
  312. OPNAME ## vc1_hor_16b_ ## NAME ## _mmx(uint8_t *dst, x86_reg stride, \
  313. const int16_t *src, int rnd) \
  314. { \
  315. int h = 8; \
  316. src -= 1; \
  317. rnd -= (-4+58+13-3)*256; /* Add -256 bias */ \
  318. __asm__ volatile( \
  319. LOAD_ROUNDER_MMX("%4") \
  320. "movq "MANGLE(ff_pw_18)", %%mm6 \n\t" \
  321. "movq "MANGLE(ff_pw_53)", %%mm5 \n\t" \
  322. ".p2align 3 \n\t" \
  323. "1: \n\t" \
  324. MSPEL_FILTER13_CORE(DONT_UNPACK, "movq 2", A1, A2, A3, A4) \
  325. NORMALIZE_MMX("$7") \
  326. /* Remove bias */ \
  327. "paddw "MANGLE(ff_pw_128)", %%mm3 \n\t" \
  328. "paddw "MANGLE(ff_pw_128)", %%mm4 \n\t" \
  329. TRANSFER_DO_PACK(OP) \
  330. "add $24, %1 \n\t" \
  331. "add %3, %2 \n\t" \
  332. "decl %0 \n\t" \
  333. "jnz 1b \n\t" \
  334. : "+r"(h), "+r" (src), "+r" (dst) \
  335. : "r"(stride), "m"(rnd) \
  336. : "memory" \
  337. ); \
  338. }
  339. /**
  340. * Macro to build the 8bits, any direction, version of vc1_put_shift[13].
  341. * Here, offset=src_stride. Parameters passed A1 to A4 must use
  342. * %3 (offset) and %4 (3*offset).
  343. *
  344. * @param NAME Either 1 or 3
  345. * @see MSPEL_FILTER13_CORE for information on A1->A4
  346. */
  347. #define MSPEL_FILTER13_8B(NAME, A1, A2, A3, A4, OP, OPNAME) \
  348. static void \
  349. OPNAME ## vc1_## NAME ## _mmx(uint8_t *dst, const uint8_t *src, \
  350. x86_reg stride, int rnd, x86_reg offset) \
  351. { \
  352. int h = 8; \
  353. src -= offset; \
  354. rnd = 32-rnd; \
  355. __asm__ volatile ( \
  356. LOAD_ROUNDER_MMX("%6") \
  357. "movq "MANGLE(ff_pw_53)", %%mm5 \n\t" \
  358. "movq "MANGLE(ff_pw_18)", %%mm6 \n\t" \
  359. ".p2align 3 \n\t" \
  360. "1: \n\t" \
  361. MSPEL_FILTER13_CORE(DO_UNPACK, "movd 1", A1, A2, A3, A4) \
  362. NORMALIZE_MMX("$6") \
  363. TRANSFER_DO_PACK(OP) \
  364. "add %5, %1 \n\t" \
  365. "add %5, %2 \n\t" \
  366. "decl %0 \n\t" \
  367. "jnz 1b \n\t" \
  368. : "+r"(h), "+r" (src), "+r" (dst) \
  369. : "r"(offset), "r"(3*offset), "g"(stride), "m"(rnd) \
  370. : "memory" \
  371. ); \
  372. }
  373. /** 1/4 shift bicubic interpolation */
  374. MSPEL_FILTER13_8B (shift1, "0(%1,%4 )", "0(%1,%3,2)", "0(%1,%3 )", "0(%1 )", OP_PUT, put_)
  375. MSPEL_FILTER13_8B (shift1, "0(%1,%4 )", "0(%1,%3,2)", "0(%1,%3 )", "0(%1 )", OP_AVG, avg_)
  376. MSPEL_FILTER13_VER_16B(shift1, "0(%1,%4 )", "0(%1,%3,2)", "0(%1,%3 )", "0(%1 )")
  377. MSPEL_FILTER13_HOR_16B(shift1, "2*3(%1)", "2*2(%1)", "2*1(%1)", "2*0(%1)", OP_PUT, put_)
  378. MSPEL_FILTER13_HOR_16B(shift1, "2*3(%1)", "2*2(%1)", "2*1(%1)", "2*0(%1)", OP_AVG, avg_)
  379. /** 3/4 shift bicubic interpolation */
  380. MSPEL_FILTER13_8B (shift3, "0(%1 )", "0(%1,%3 )", "0(%1,%3,2)", "0(%1,%4 )", OP_PUT, put_)
  381. MSPEL_FILTER13_8B (shift3, "0(%1 )", "0(%1,%3 )", "0(%1,%3,2)", "0(%1,%4 )", OP_AVG, avg_)
  382. MSPEL_FILTER13_VER_16B(shift3, "0(%1 )", "0(%1,%3 )", "0(%1,%3,2)", "0(%1,%4 )")
  383. MSPEL_FILTER13_HOR_16B(shift3, "2*0(%1)", "2*1(%1)", "2*2(%1)", "2*3(%1)", OP_PUT, put_)
  384. MSPEL_FILTER13_HOR_16B(shift3, "2*0(%1)", "2*1(%1)", "2*2(%1)", "2*3(%1)", OP_AVG, avg_)
  385. typedef void (*vc1_mspel_mc_filter_ver_16bits)(int16_t *dst, const uint8_t *src, x86_reg src_stride, int rnd, int64_t shift);
  386. typedef void (*vc1_mspel_mc_filter_hor_16bits)(uint8_t *dst, x86_reg dst_stride, const int16_t *src, int rnd);
  387. typedef void (*vc1_mspel_mc_filter_8bits)(uint8_t *dst, const uint8_t *src, x86_reg stride, int rnd, x86_reg offset);
  388. /**
  389. * Interpolate fractional pel values by applying proper vertical then
  390. * horizontal filter.
  391. *
  392. * @param dst Destination buffer for interpolated pels.
  393. * @param src Source buffer.
  394. * @param stride Stride for both src and dst buffers.
  395. * @param hmode Horizontal filter (expressed in quarter pixels shift).
  396. * @param hmode Vertical filter.
  397. * @param rnd Rounding bias.
  398. */
  399. #define VC1_MSPEL_MC(OP)\
  400. static void OP ## vc1_mspel_mc(uint8_t *dst, const uint8_t *src, int stride,\
  401. int hmode, int vmode, int rnd)\
  402. {\
  403. static const vc1_mspel_mc_filter_ver_16bits vc1_put_shift_ver_16bits[] =\
  404. { NULL, vc1_put_ver_16b_shift1_mmx, vc1_put_ver_16b_shift2_mmx, vc1_put_ver_16b_shift3_mmx };\
  405. static const vc1_mspel_mc_filter_hor_16bits vc1_put_shift_hor_16bits[] =\
  406. { NULL, OP ## vc1_hor_16b_shift1_mmx, OP ## vc1_hor_16b_shift2_mmx, OP ## vc1_hor_16b_shift3_mmx };\
  407. static const vc1_mspel_mc_filter_8bits vc1_put_shift_8bits[] =\
  408. { NULL, OP ## vc1_shift1_mmx, OP ## vc1_shift2_mmx, OP ## vc1_shift3_mmx };\
  409. \
  410. __asm__ volatile(\
  411. "pxor %%mm0, %%mm0 \n\t"\
  412. ::: "memory"\
  413. );\
  414. \
  415. if (vmode) { /* Vertical filter to apply */\
  416. if (hmode) { /* Horizontal filter to apply, output to tmp */\
  417. static const int shift_value[] = { 0, 5, 1, 5 };\
  418. int shift = (shift_value[hmode]+shift_value[vmode])>>1;\
  419. int r;\
  420. DECLARE_ALIGNED(16, int16_t, tmp)[12*8];\
  421. \
  422. r = (1<<(shift-1)) + rnd-1;\
  423. vc1_put_shift_ver_16bits[vmode](tmp, src-1, stride, r, shift);\
  424. \
  425. vc1_put_shift_hor_16bits[hmode](dst, stride, tmp+1, 64-rnd);\
  426. return;\
  427. }\
  428. else { /* No horizontal filter, output 8 lines to dst */\
  429. vc1_put_shift_8bits[vmode](dst, src, stride, 1-rnd, stride);\
  430. return;\
  431. }\
  432. }\
  433. \
  434. /* Horizontal mode with no vertical mode */\
  435. vc1_put_shift_8bits[hmode](dst, src, stride, rnd, 1);\
  436. }
  437. VC1_MSPEL_MC(put_)
  438. VC1_MSPEL_MC(avg_)
  439. /** Macro to ease bicubic filter interpolation functions declarations */
  440. #define DECLARE_FUNCTION(a, b) \
  441. static void put_vc1_mspel_mc ## a ## b ## _mmx(uint8_t *dst, \
  442. const uint8_t *src, \
  443. ptrdiff_t stride, \
  444. int rnd) \
  445. { \
  446. put_vc1_mspel_mc(dst, src, stride, a, b, rnd); \
  447. }\
  448. static void avg_vc1_mspel_mc ## a ## b ## _mmxext(uint8_t *dst, \
  449. const uint8_t *src, \
  450. ptrdiff_t stride, \
  451. int rnd) \
  452. { \
  453. avg_vc1_mspel_mc(dst, src, stride, a, b, rnd); \
  454. }
  455. DECLARE_FUNCTION(0, 1)
  456. DECLARE_FUNCTION(0, 2)
  457. DECLARE_FUNCTION(0, 3)
  458. DECLARE_FUNCTION(1, 0)
  459. DECLARE_FUNCTION(1, 1)
  460. DECLARE_FUNCTION(1, 2)
  461. DECLARE_FUNCTION(1, 3)
  462. DECLARE_FUNCTION(2, 0)
  463. DECLARE_FUNCTION(2, 1)
  464. DECLARE_FUNCTION(2, 2)
  465. DECLARE_FUNCTION(2, 3)
  466. DECLARE_FUNCTION(3, 0)
  467. DECLARE_FUNCTION(3, 1)
  468. DECLARE_FUNCTION(3, 2)
  469. DECLARE_FUNCTION(3, 3)
  470. static void vc1_inv_trans_4x4_dc_mmxext(uint8_t *dest, int linesize,
  471. int16_t *block)
  472. {
  473. int dc = block[0];
  474. dc = (17 * dc + 4) >> 3;
  475. dc = (17 * dc + 64) >> 7;
  476. __asm__ volatile(
  477. "movd %0, %%mm0 \n\t"
  478. "pshufw $0, %%mm0, %%mm0 \n\t"
  479. "pxor %%mm1, %%mm1 \n\t"
  480. "psubw %%mm0, %%mm1 \n\t"
  481. "packuswb %%mm0, %%mm0 \n\t"
  482. "packuswb %%mm1, %%mm1 \n\t"
  483. ::"r"(dc)
  484. );
  485. __asm__ volatile(
  486. "movd %0, %%mm2 \n\t"
  487. "movd %1, %%mm3 \n\t"
  488. "movd %2, %%mm4 \n\t"
  489. "movd %3, %%mm5 \n\t"
  490. "paddusb %%mm0, %%mm2 \n\t"
  491. "paddusb %%mm0, %%mm3 \n\t"
  492. "paddusb %%mm0, %%mm4 \n\t"
  493. "paddusb %%mm0, %%mm5 \n\t"
  494. "psubusb %%mm1, %%mm2 \n\t"
  495. "psubusb %%mm1, %%mm3 \n\t"
  496. "psubusb %%mm1, %%mm4 \n\t"
  497. "psubusb %%mm1, %%mm5 \n\t"
  498. "movd %%mm2, %0 \n\t"
  499. "movd %%mm3, %1 \n\t"
  500. "movd %%mm4, %2 \n\t"
  501. "movd %%mm5, %3 \n\t"
  502. :"+m"(*(uint32_t*)(dest+0*linesize)),
  503. "+m"(*(uint32_t*)(dest+1*linesize)),
  504. "+m"(*(uint32_t*)(dest+2*linesize)),
  505. "+m"(*(uint32_t*)(dest+3*linesize))
  506. );
  507. }
  508. static void vc1_inv_trans_4x8_dc_mmxext(uint8_t *dest, int linesize,
  509. int16_t *block)
  510. {
  511. int dc = block[0];
  512. dc = (17 * dc + 4) >> 3;
  513. dc = (12 * dc + 64) >> 7;
  514. __asm__ volatile(
  515. "movd %0, %%mm0 \n\t"
  516. "pshufw $0, %%mm0, %%mm0 \n\t"
  517. "pxor %%mm1, %%mm1 \n\t"
  518. "psubw %%mm0, %%mm1 \n\t"
  519. "packuswb %%mm0, %%mm0 \n\t"
  520. "packuswb %%mm1, %%mm1 \n\t"
  521. ::"r"(dc)
  522. );
  523. __asm__ volatile(
  524. "movd %0, %%mm2 \n\t"
  525. "movd %1, %%mm3 \n\t"
  526. "movd %2, %%mm4 \n\t"
  527. "movd %3, %%mm5 \n\t"
  528. "paddusb %%mm0, %%mm2 \n\t"
  529. "paddusb %%mm0, %%mm3 \n\t"
  530. "paddusb %%mm0, %%mm4 \n\t"
  531. "paddusb %%mm0, %%mm5 \n\t"
  532. "psubusb %%mm1, %%mm2 \n\t"
  533. "psubusb %%mm1, %%mm3 \n\t"
  534. "psubusb %%mm1, %%mm4 \n\t"
  535. "psubusb %%mm1, %%mm5 \n\t"
  536. "movd %%mm2, %0 \n\t"
  537. "movd %%mm3, %1 \n\t"
  538. "movd %%mm4, %2 \n\t"
  539. "movd %%mm5, %3 \n\t"
  540. :"+m"(*(uint32_t*)(dest+0*linesize)),
  541. "+m"(*(uint32_t*)(dest+1*linesize)),
  542. "+m"(*(uint32_t*)(dest+2*linesize)),
  543. "+m"(*(uint32_t*)(dest+3*linesize))
  544. );
  545. dest += 4*linesize;
  546. __asm__ volatile(
  547. "movd %0, %%mm2 \n\t"
  548. "movd %1, %%mm3 \n\t"
  549. "movd %2, %%mm4 \n\t"
  550. "movd %3, %%mm5 \n\t"
  551. "paddusb %%mm0, %%mm2 \n\t"
  552. "paddusb %%mm0, %%mm3 \n\t"
  553. "paddusb %%mm0, %%mm4 \n\t"
  554. "paddusb %%mm0, %%mm5 \n\t"
  555. "psubusb %%mm1, %%mm2 \n\t"
  556. "psubusb %%mm1, %%mm3 \n\t"
  557. "psubusb %%mm1, %%mm4 \n\t"
  558. "psubusb %%mm1, %%mm5 \n\t"
  559. "movd %%mm2, %0 \n\t"
  560. "movd %%mm3, %1 \n\t"
  561. "movd %%mm4, %2 \n\t"
  562. "movd %%mm5, %3 \n\t"
  563. :"+m"(*(uint32_t*)(dest+0*linesize)),
  564. "+m"(*(uint32_t*)(dest+1*linesize)),
  565. "+m"(*(uint32_t*)(dest+2*linesize)),
  566. "+m"(*(uint32_t*)(dest+3*linesize))
  567. );
  568. }
  569. static void vc1_inv_trans_8x4_dc_mmxext(uint8_t *dest, int linesize,
  570. int16_t *block)
  571. {
  572. int dc = block[0];
  573. dc = ( 3 * dc + 1) >> 1;
  574. dc = (17 * dc + 64) >> 7;
  575. __asm__ volatile(
  576. "movd %0, %%mm0 \n\t"
  577. "pshufw $0, %%mm0, %%mm0 \n\t"
  578. "pxor %%mm1, %%mm1 \n\t"
  579. "psubw %%mm0, %%mm1 \n\t"
  580. "packuswb %%mm0, %%mm0 \n\t"
  581. "packuswb %%mm1, %%mm1 \n\t"
  582. ::"r"(dc)
  583. );
  584. __asm__ volatile(
  585. "movq %0, %%mm2 \n\t"
  586. "movq %1, %%mm3 \n\t"
  587. "movq %2, %%mm4 \n\t"
  588. "movq %3, %%mm5 \n\t"
  589. "paddusb %%mm0, %%mm2 \n\t"
  590. "paddusb %%mm0, %%mm3 \n\t"
  591. "paddusb %%mm0, %%mm4 \n\t"
  592. "paddusb %%mm0, %%mm5 \n\t"
  593. "psubusb %%mm1, %%mm2 \n\t"
  594. "psubusb %%mm1, %%mm3 \n\t"
  595. "psubusb %%mm1, %%mm4 \n\t"
  596. "psubusb %%mm1, %%mm5 \n\t"
  597. "movq %%mm2, %0 \n\t"
  598. "movq %%mm3, %1 \n\t"
  599. "movq %%mm4, %2 \n\t"
  600. "movq %%mm5, %3 \n\t"
  601. :"+m"(*(uint32_t*)(dest+0*linesize)),
  602. "+m"(*(uint32_t*)(dest+1*linesize)),
  603. "+m"(*(uint32_t*)(dest+2*linesize)),
  604. "+m"(*(uint32_t*)(dest+3*linesize))
  605. );
  606. }
  607. static void vc1_inv_trans_8x8_dc_mmxext(uint8_t *dest, int linesize,
  608. int16_t *block)
  609. {
  610. int dc = block[0];
  611. dc = (3 * dc + 1) >> 1;
  612. dc = (3 * dc + 16) >> 5;
  613. __asm__ volatile(
  614. "movd %0, %%mm0 \n\t"
  615. "pshufw $0, %%mm0, %%mm0 \n\t"
  616. "pxor %%mm1, %%mm1 \n\t"
  617. "psubw %%mm0, %%mm1 \n\t"
  618. "packuswb %%mm0, %%mm0 \n\t"
  619. "packuswb %%mm1, %%mm1 \n\t"
  620. ::"r"(dc)
  621. );
  622. __asm__ volatile(
  623. "movq %0, %%mm2 \n\t"
  624. "movq %1, %%mm3 \n\t"
  625. "movq %2, %%mm4 \n\t"
  626. "movq %3, %%mm5 \n\t"
  627. "paddusb %%mm0, %%mm2 \n\t"
  628. "paddusb %%mm0, %%mm3 \n\t"
  629. "paddusb %%mm0, %%mm4 \n\t"
  630. "paddusb %%mm0, %%mm5 \n\t"
  631. "psubusb %%mm1, %%mm2 \n\t"
  632. "psubusb %%mm1, %%mm3 \n\t"
  633. "psubusb %%mm1, %%mm4 \n\t"
  634. "psubusb %%mm1, %%mm5 \n\t"
  635. "movq %%mm2, %0 \n\t"
  636. "movq %%mm3, %1 \n\t"
  637. "movq %%mm4, %2 \n\t"
  638. "movq %%mm5, %3 \n\t"
  639. :"+m"(*(uint32_t*)(dest+0*linesize)),
  640. "+m"(*(uint32_t*)(dest+1*linesize)),
  641. "+m"(*(uint32_t*)(dest+2*linesize)),
  642. "+m"(*(uint32_t*)(dest+3*linesize))
  643. );
  644. dest += 4*linesize;
  645. __asm__ volatile(
  646. "movq %0, %%mm2 \n\t"
  647. "movq %1, %%mm3 \n\t"
  648. "movq %2, %%mm4 \n\t"
  649. "movq %3, %%mm5 \n\t"
  650. "paddusb %%mm0, %%mm2 \n\t"
  651. "paddusb %%mm0, %%mm3 \n\t"
  652. "paddusb %%mm0, %%mm4 \n\t"
  653. "paddusb %%mm0, %%mm5 \n\t"
  654. "psubusb %%mm1, %%mm2 \n\t"
  655. "psubusb %%mm1, %%mm3 \n\t"
  656. "psubusb %%mm1, %%mm4 \n\t"
  657. "psubusb %%mm1, %%mm5 \n\t"
  658. "movq %%mm2, %0 \n\t"
  659. "movq %%mm3, %1 \n\t"
  660. "movq %%mm4, %2 \n\t"
  661. "movq %%mm5, %3 \n\t"
  662. :"+m"(*(uint32_t*)(dest+0*linesize)),
  663. "+m"(*(uint32_t*)(dest+1*linesize)),
  664. "+m"(*(uint32_t*)(dest+2*linesize)),
  665. "+m"(*(uint32_t*)(dest+3*linesize))
  666. );
  667. }
  668. av_cold void ff_vc1dsp_init_mmx(VC1DSPContext *dsp)
  669. {
  670. dsp->put_vc1_mspel_pixels_tab[ 0] = ff_put_vc1_mspel_mc00_mmx;
  671. dsp->put_vc1_mspel_pixels_tab[ 4] = put_vc1_mspel_mc01_mmx;
  672. dsp->put_vc1_mspel_pixels_tab[ 8] = put_vc1_mspel_mc02_mmx;
  673. dsp->put_vc1_mspel_pixels_tab[12] = put_vc1_mspel_mc03_mmx;
  674. dsp->put_vc1_mspel_pixels_tab[ 1] = put_vc1_mspel_mc10_mmx;
  675. dsp->put_vc1_mspel_pixels_tab[ 5] = put_vc1_mspel_mc11_mmx;
  676. dsp->put_vc1_mspel_pixels_tab[ 9] = put_vc1_mspel_mc12_mmx;
  677. dsp->put_vc1_mspel_pixels_tab[13] = put_vc1_mspel_mc13_mmx;
  678. dsp->put_vc1_mspel_pixels_tab[ 2] = put_vc1_mspel_mc20_mmx;
  679. dsp->put_vc1_mspel_pixels_tab[ 6] = put_vc1_mspel_mc21_mmx;
  680. dsp->put_vc1_mspel_pixels_tab[10] = put_vc1_mspel_mc22_mmx;
  681. dsp->put_vc1_mspel_pixels_tab[14] = put_vc1_mspel_mc23_mmx;
  682. dsp->put_vc1_mspel_pixels_tab[ 3] = put_vc1_mspel_mc30_mmx;
  683. dsp->put_vc1_mspel_pixels_tab[ 7] = put_vc1_mspel_mc31_mmx;
  684. dsp->put_vc1_mspel_pixels_tab[11] = put_vc1_mspel_mc32_mmx;
  685. dsp->put_vc1_mspel_pixels_tab[15] = put_vc1_mspel_mc33_mmx;
  686. }
  687. av_cold void ff_vc1dsp_init_mmxext(VC1DSPContext *dsp)
  688. {
  689. dsp->avg_vc1_mspel_pixels_tab[ 4] = avg_vc1_mspel_mc01_mmxext;
  690. dsp->avg_vc1_mspel_pixels_tab[ 8] = avg_vc1_mspel_mc02_mmxext;
  691. dsp->avg_vc1_mspel_pixels_tab[12] = avg_vc1_mspel_mc03_mmxext;
  692. dsp->avg_vc1_mspel_pixels_tab[ 1] = avg_vc1_mspel_mc10_mmxext;
  693. dsp->avg_vc1_mspel_pixels_tab[ 5] = avg_vc1_mspel_mc11_mmxext;
  694. dsp->avg_vc1_mspel_pixels_tab[ 9] = avg_vc1_mspel_mc12_mmxext;
  695. dsp->avg_vc1_mspel_pixels_tab[13] = avg_vc1_mspel_mc13_mmxext;
  696. dsp->avg_vc1_mspel_pixels_tab[ 2] = avg_vc1_mspel_mc20_mmxext;
  697. dsp->avg_vc1_mspel_pixels_tab[ 6] = avg_vc1_mspel_mc21_mmxext;
  698. dsp->avg_vc1_mspel_pixels_tab[10] = avg_vc1_mspel_mc22_mmxext;
  699. dsp->avg_vc1_mspel_pixels_tab[14] = avg_vc1_mspel_mc23_mmxext;
  700. dsp->avg_vc1_mspel_pixels_tab[ 3] = avg_vc1_mspel_mc30_mmxext;
  701. dsp->avg_vc1_mspel_pixels_tab[ 7] = avg_vc1_mspel_mc31_mmxext;
  702. dsp->avg_vc1_mspel_pixels_tab[11] = avg_vc1_mspel_mc32_mmxext;
  703. dsp->avg_vc1_mspel_pixels_tab[15] = avg_vc1_mspel_mc33_mmxext;
  704. dsp->vc1_inv_trans_8x8_dc = vc1_inv_trans_8x8_dc_mmxext;
  705. dsp->vc1_inv_trans_4x8_dc = vc1_inv_trans_4x8_dc_mmxext;
  706. dsp->vc1_inv_trans_8x4_dc = vc1_inv_trans_8x4_dc_mmxext;
  707. dsp->vc1_inv_trans_4x4_dc = vc1_inv_trans_4x4_dc_mmxext;
  708. }
  709. #endif /* HAVE_INLINE_ASM */