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FFmpeg/libavcodec/sparc/vis.h

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  1. /*

  2.  * vis.h

  3.  * Copyright (C) 2003 David S. Miller <davem@redhat.com>

  4.  *

  5.  * This file is part of FFmpeg.

  6.  *

  7.  * FFmpeg is free software; you can redistribute it and/or

  8.  * modify it under the terms of the GNU Lesser General Public

  9.  * License as published by the Free Software Foundation; either

  10.  * version 2.1 of the License, or (at your option) any later version.

  11.  *

  12.  * FFmpeg is distributed in the hope that it will be useful,

  13.  * but WITHOUT ANY WARRANTY; without even the implied warranty of

  14.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

  15.  * Lesser General Public License for more details.

  16.  *

  17.  * You should have received a copy of the GNU Lesser General Public

  18.  * License along with FFmpeg; if not, write to the Free Software

  19.  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA

  20.  */

  21. 

  22. /* You may be asking why I hard-code the instruction opcodes and don't

  23.  * use the normal VIS assembler mnenomics for the VIS instructions.

  24.  *

  25.  * The reason is that Sun, in their infinite wisdom, decided that a binary

  26.  * using a VIS instruction will cause it to be marked (in the ELF headers)

  27.  * as doing so, and this prevents the OS from loading such binaries if the

  28.  * current cpu doesn't have VIS.  There is no way to easily override this

  29.  * behavior of the assembler that I am aware of.

  30.  *

  31.  * This totally defeats what libmpeg2 is trying to do which is allow a

  32.  * single binary to be created, and then detect the availability of VIS

  33.  * at runtime.

  34.  *

  35.  * I'm not saying that tainting the binary by default is bad, rather I'm

  36.  * saying that not providing a way to override this easily unnecessarily

  37.  * ties people's hands.

  38.  *

  39.  * Thus, we do the opcode encoding by hand and output 32-bit words in

  40.  * the assembler to keep the binary from becoming tainted.

  41.  */

  42. 

  43. #ifndef AVCODEC_SPARC_VIS_H

  44. #define AVCODEC_SPARC_VIS_H

  45. 

  46. #define vis_opc_base    ((0x1 << 31) | (0x36 << 19))

  47. #define vis_opf(X)      ((X) << 5)

  48. #define vis_sreg(X)     (X)

  49. #define vis_dreg(X)     (((X)&0x1f)|((X)>>5))

  50. #define vis_rs1_s(X)    (vis_sreg(X) << 14)

  51. #define vis_rs1_d(X)    (vis_dreg(X) << 14)

  52. #define vis_rs2_s(X)    (vis_sreg(X) << 0)

  53. #define vis_rs2_d(X)    (vis_dreg(X) << 0)

  54. #define vis_rd_s(X)     (vis_sreg(X) << 25)

  55. #define vis_rd_d(X)     (vis_dreg(X) << 25)

  56. 

  57. #define vis_ss2s(opf,rs1,rs2,rd) \

  58.         __asm__ volatile (".word %0" \

  59.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  60.                                        vis_rs1_s(rs1) | \

  61.                                        vis_rs2_s(rs2) | \

  62.                                        vis_rd_s(rd)))

  63. 

  64. #define vis_dd2d(opf,rs1,rs2,rd) \

  65.         __asm__ volatile (".word %0" \

  66.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  67.                                        vis_rs1_d(rs1) | \

  68.                                        vis_rs2_d(rs2) | \

  69.                                        vis_rd_d(rd)))

  70. 

  71. #define vis_ss2d(opf,rs1,rs2,rd) \

  72.         __asm__ volatile (".word %0" \

  73.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  74.                                        vis_rs1_s(rs1) | \

  75.                                        vis_rs2_s(rs2) | \

  76.                                        vis_rd_d(rd)))

  77. 

  78. #define vis_sd2d(opf,rs1,rs2,rd) \

  79.         __asm__ volatile (".word %0" \

  80.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  81.                                        vis_rs1_s(rs1) | \

  82.                                        vis_rs2_d(rs2) | \

  83.                                        vis_rd_d(rd)))

  84. 

  85. #define vis_d2s(opf,rs2,rd) \

  86.         __asm__ volatile (".word %0" \

  87.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  88.                                        vis_rs2_d(rs2) | \

  89.                                        vis_rd_s(rd)))

  90. 

  91. #define vis_s2d(opf,rs2,rd) \

  92.         __asm__ volatile (".word %0" \

  93.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  94.                                        vis_rs2_s(rs2) | \

  95.                                        vis_rd_d(rd)))

  96. 

  97. #define vis_d12d(opf,rs1,rd) \

  98.         __asm__ volatile (".word %0" \

  99.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  100.                                        vis_rs1_d(rs1) | \

  101.                                        vis_rd_d(rd)))

  102. 

  103. #define vis_d22d(opf,rs2,rd) \

  104.         __asm__ volatile (".word %0" \

  105.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  106.                                        vis_rs2_d(rs2) | \

  107.                                        vis_rd_d(rd)))

  108. 

  109. #define vis_s12s(opf,rs1,rd) \

  110.         __asm__ volatile (".word %0" \

  111.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  112.                                        vis_rs1_s(rs1) | \

  113.                                        vis_rd_s(rd)))

  114. 

  115. #define vis_s22s(opf,rs2,rd) \

  116.         __asm__ volatile (".word %0" \

  117.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  118.                                        vis_rs2_s(rs2) | \

  119.                                        vis_rd_s(rd)))

  120. 

  121. #define vis_s(opf,rd) \

  122.         __asm__ volatile (".word %0" \

  123.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  124.                                        vis_rd_s(rd)))

  125. 

  126. #define vis_d(opf,rd) \

  127.         __asm__ volatile (".word %0" \

  128.                               : : "i" (vis_opc_base | vis_opf(opf) | \

  129.                                        vis_rd_d(rd)))

  130. 

  131. #define vis_r2m(op,rd,mem) \

  132.         __asm__ volatile (#op "\t%%f" #rd ", [%0]" : : "r" (&(mem)) )

  133. 

  134. #define vis_r2m_2(op,rd,mem1,mem2) \

  135.         __asm__ volatile (#op "\t%%f" #rd ", [%0 + %1]" : : "r" (mem1), "r" (mem2) )

  136. 

  137. #define vis_m2r(op,mem,rd) \

  138.         __asm__ volatile (#op "\t[%0], %%f" #rd : : "r" (&(mem)) )

  139. 

  140. #define vis_m2r_2(op,mem1,mem2,rd) \

  141.         __asm__ volatile (#op "\t[%0 + %1], %%f" #rd : : "r" (mem1), "r" (mem2) )

  142. 

  143. static inline void vis_set_gsr(unsigned int _val)

  144. {

  145.         register unsigned int val __asm__("g1");

  146. 

  147.         val = _val;

  148.         __asm__ volatile(".word 0xa7804000"

  149.                              : : "r" (val));

  150. }

  151. 

  152. #define VIS_GSR_ALIGNADDR_MASK          0x0000007

  153. #define VIS_GSR_ALIGNADDR_SHIFT         0

  154. #define VIS_GSR_SCALEFACT_MASK          0x0000078

  155. #define VIS_GSR_SCALEFACT_SHIFT         3

  156. 

  157. #define vis_ld32(mem,rs1)               vis_m2r(ld, mem, rs1)

  158. #define vis_ld32_2(mem1,mem2,rs1)       vis_m2r_2(ld, mem1, mem2, rs1)

  159. #define vis_st32(rs1,mem)               vis_r2m(st, rs1, mem)

  160. #define vis_st32_2(rs1,mem1,mem2)       vis_r2m_2(st, rs1, mem1, mem2)

  161. #define vis_ld64(mem,rs1)               vis_m2r(ldd, mem, rs1)

  162. #define vis_ld64_2(mem1,mem2,rs1)       vis_m2r_2(ldd, mem1, mem2, rs1)

  163. #define vis_st64(rs1,mem)               vis_r2m(std, rs1, mem)

  164. #define vis_st64_2(rs1,mem1,mem2)       vis_r2m_2(std, rs1, mem1, mem2)

  165. 

  166. #define vis_ldblk(mem, rd) \

  167. do {        register void *__mem __asm__("g1"); \

  168.         __mem = &(mem); \

  169.         __asm__ volatile(".word 0xc1985e00 | %1" \

  170.                              : \

  171.                              : "r" (__mem), \

  172.                                "i" (vis_rd_d(rd)) \

  173.                              : "memory"); \

  174. } while (0)

  175. 

  176. #define vis_stblk(rd, mem) \

  177. do {        register void *__mem __asm__("g1"); \

  178.         __mem = &(mem); \

  179.         __asm__ volatile(".word 0xc1b85e00 | %1" \

  180.                              : \

  181.                              : "r" (__mem), \

  182.                                "i" (vis_rd_d(rd)) \

  183.                              : "memory"); \

  184. } while (0)

  185. 

  186. #define vis_membar_storestore()        \

  187.         __asm__ volatile(".word 0x8143e008" : : : "memory")

  188. 

  189. #define vis_membar_sync()        \

  190.         __asm__ volatile(".word 0x8143e040" : : : "memory")

  191. 

  192. /* 16 and 32 bit partitioned addition and subtraction.  The normal

  193.  * versions perform 4 16-bit or 2 32-bit additions or subtractions.

  194.  * The 's' versions perform 2 16-bit or 1 32-bit additions or

  195.  * subtractions.

  196.  */

  197. 

  198. #define vis_padd16(rs1,rs2,rd)          vis_dd2d(0x50, rs1, rs2, rd)

  199. #define vis_padd16s(rs1,rs2,rd)         vis_ss2s(0x51, rs1, rs2, rd)

  200. #define vis_padd32(rs1,rs2,rd)          vis_dd2d(0x52, rs1, rs2, rd)

  201. #define vis_padd32s(rs1,rs2,rd)         vis_ss2s(0x53, rs1, rs2, rd)

  202. #define vis_psub16(rs1,rs2,rd)          vis_dd2d(0x54, rs1, rs2, rd)

  203. #define vis_psub16s(rs1,rs2,rd)         vis_ss2s(0x55, rs1, rs2, rd)

  204. #define vis_psub32(rs1,rs2,rd)          vis_dd2d(0x56, rs1, rs2, rd)

  205. #define vis_psub32s(rs1,rs2,rd)         vis_ss2s(0x57, rs1, rs2, rd)

  206. 

  207. /* Pixel formatting instructions.  */

  208. 

  209. #define vis_pack16(rs2,rd)              vis_d2s( 0x3b,      rs2, rd)

  210. #define vis_pack32(rs1,rs2,rd)          vis_dd2d(0x3a, rs1, rs2, rd)

  211. #define vis_packfix(rs2,rd)             vis_d2s( 0x3d,      rs2, rd)

  212. #define vis_expand(rs2,rd)              vis_s2d( 0x4d,      rs2, rd)

  213. #define vis_pmerge(rs1,rs2,rd)          vis_ss2d(0x4b, rs1, rs2, rd)

  214. 

  215. /* Partitioned multiply instructions.  */

  216. 

  217. #define vis_mul8x16(rs1,rs2,rd)         vis_sd2d(0x31, rs1, rs2, rd)

  218. #define vis_mul8x16au(rs1,rs2,rd)       vis_ss2d(0x33, rs1, rs2, rd)

  219. #define vis_mul8x16al(rs1,rs2,rd)       vis_ss2d(0x35, rs1, rs2, rd)

  220. #define vis_mul8sux16(rs1,rs2,rd)       vis_dd2d(0x36, rs1, rs2, rd)

  221. #define vis_mul8ulx16(rs1,rs2,rd)       vis_dd2d(0x37, rs1, rs2, rd)

  222. #define vis_muld8sux16(rs1,rs2,rd)      vis_ss2d(0x38, rs1, rs2, rd)

  223. #define vis_muld8ulx16(rs1,rs2,rd)      vis_ss2d(0x39, rs1, rs2, rd)

  224. 

  225. /* Alignment instructions.  */

  226. 

  227. static inline void *vis_alignaddr(void *_ptr)

  228. {

  229.         register void *ptr __asm__("g1");

  230. 

  231.         ptr = _ptr;

  232. 

  233.         __asm__ volatile(".word %2"

  234.                              : "=&r" (ptr)

  235.                              : "0" (ptr),

  236.                                "i" (vis_opc_base | vis_opf(0x18) |

  237.                                     vis_rs1_s(1) |

  238.                                     vis_rs2_s(0) |

  239.                                     vis_rd_s(1)));

  240. 

  241.         return ptr;

  242. }

  243. 

  244. static inline void vis_alignaddr_g0(void *_ptr)

  245. {

  246.         register void *ptr __asm__("g1");

  247. 

  248.         ptr = _ptr;

  249. 

  250.         __asm__ volatile(".word %2"

  251.                              : "=&r" (ptr)

  252.                              : "0" (ptr),

  253.                                "i" (vis_opc_base | vis_opf(0x18) |

  254.                                     vis_rs1_s(1) |

  255.                                     vis_rs2_s(0) |

  256.                                     vis_rd_s(0)));

  257. }

  258. 

  259. static inline void *vis_alignaddrl(void *_ptr)

  260. {

  261.         register void *ptr __asm__("g1");

  262. 

  263.         ptr = _ptr;

  264. 

  265.         __asm__ volatile(".word %2"

  266.                              : "=&r" (ptr)

  267.                              : "0" (ptr),

  268.                                "i" (vis_opc_base | vis_opf(0x19) |

  269.                                     vis_rs1_s(1) |

  270.                                     vis_rs2_s(0) |

  271.                                     vis_rd_s(1)));

  272. 

  273.         return ptr;

  274. }

  275. 

  276. static inline void vis_alignaddrl_g0(void *_ptr)

  277. {

  278.         register void *ptr __asm__("g1");

  279. 

  280.         ptr = _ptr;

  281. 

  282.         __asm__ volatile(".word %2"

  283.                              : "=&r" (ptr)

  284.                              : "0" (ptr),

  285.                                "i" (vis_opc_base | vis_opf(0x19) |

  286.                                     vis_rs1_s(1) |

  287.                                     vis_rs2_s(0) |

  288.                                     vis_rd_s(0)));

  289. }

  290. 

  291. #define vis_faligndata(rs1,rs2,rd)        vis_dd2d(0x48, rs1, rs2, rd)

  292. 

  293. /* Logical operate instructions.  */

  294. 

  295. #define vis_fzero(rd)                   vis_d(   0x60,           rd)

  296. #define vis_fzeros(rd)                  vis_s(   0x61,           rd)

  297. #define vis_fone(rd)                    vis_d(   0x7e,           rd)

  298. #define vis_fones(rd)                   vis_s(   0x7f,           rd)

  299. #define vis_src1(rs1,rd)                vis_d12d(0x74, rs1,      rd)

  300. #define vis_src1s(rs1,rd)               vis_s12s(0x75, rs1,      rd)

  301. #define vis_src2(rs2,rd)                vis_d22d(0x78,      rs2, rd)

  302. #define vis_src2s(rs2,rd)               vis_s22s(0x79,      rs2, rd)

  303. #define vis_not1(rs1,rd)                vis_d12d(0x6a, rs1,      rd)

  304. #define vis_not1s(rs1,rd)               vis_s12s(0x6b, rs1,      rd)

  305. #define vis_not2(rs2,rd)                vis_d22d(0x66,      rs2, rd)

  306. #define vis_not2s(rs2,rd)               vis_s22s(0x67,      rs2, rd)

  307. #define vis_or(rs1,rs2,rd)              vis_dd2d(0x7c, rs1, rs2, rd)

  308. #define vis_ors(rs1,rs2,rd)             vis_ss2s(0x7d, rs1, rs2, rd)

  309. #define vis_nor(rs1,rs2,rd)             vis_dd2d(0x62, rs1, rs2, rd)

  310. #define vis_nors(rs1,rs2,rd)            vis_ss2s(0x63, rs1, rs2, rd)

  311. #define vis_and(rs1,rs2,rd)             vis_dd2d(0x70, rs1, rs2, rd)

  312. #define vis_ands(rs1,rs2,rd)            vis_ss2s(0x71, rs1, rs2, rd)

  313. #define vis_nand(rs1,rs2,rd)            vis_dd2d(0x6e, rs1, rs2, rd)

  314. #define vis_nands(rs1,rs2,rd)           vis_ss2s(0x6f, rs1, rs2, rd)

  315. #define vis_xor(rs1,rs2,rd)             vis_dd2d(0x6c, rs1, rs2, rd)

  316. #define vis_xors(rs1,rs2,rd)            vis_ss2s(0x6d, rs1, rs2, rd)

  317. #define vis_xnor(rs1,rs2,rd)            vis_dd2d(0x72, rs1, rs2, rd)

  318. #define vis_xnors(rs1,rs2,rd)           vis_ss2s(0x73, rs1, rs2, rd)

  319. #define vis_ornot1(rs1,rs2,rd)          vis_dd2d(0x7a, rs1, rs2, rd)

  320. #define vis_ornot1s(rs1,rs2,rd)         vis_ss2s(0x7b, rs1, rs2, rd)

  321. #define vis_ornot2(rs1,rs2,rd)          vis_dd2d(0x76, rs1, rs2, rd)

  322. #define vis_ornot2s(rs1,rs2,rd)         vis_ss2s(0x77, rs1, rs2, rd)

  323. #define vis_andnot1(rs1,rs2,rd)         vis_dd2d(0x68, rs1, rs2, rd)

  324. #define vis_andnot1s(rs1,rs2,rd)        vis_ss2s(0x69, rs1, rs2, rd)

  325. #define vis_andnot2(rs1,rs2,rd)         vis_dd2d(0x64, rs1, rs2, rd)

  326. #define vis_andnot2s(rs1,rs2,rd)        vis_ss2s(0x65, rs1, rs2, rd)

  327. 

  328. /* Pixel component distance.  */

  329. 

  330. #define vis_pdist(rs1,rs2,rd)           vis_dd2d(0x3e, rs1, rs2, rd)

  331. 

  332. #endif /* AVCODEC_SPARC_VIS_H */