3 Commits (f973a85d4af67165dd1661c347f33ac5d1ef51a3)

Author SHA1 Message Date
  Christophe GISQUET 2130bd8f5b rv40dsp x86: use only one register, for both increment and loop counter 13 years ago
  Christophe GISQUET 272b252c01 rv40dsp: implement prescaled versions for biweight. 13 years ago
  Christophe Gisquet e5c9de2ab7 rv40: x86 SIMD for biweight 14 years ago