@@ -40,8 +40,8 @@ | |||||
#define AV_VERSION(a, b, c) AV_VERSION_DOT(a, b, c) | #define AV_VERSION(a, b, c) AV_VERSION_DOT(a, b, c) | ||||
#define LIBAVUTIL_VERSION_MAJOR 51 | #define LIBAVUTIL_VERSION_MAJOR 51 | ||||
#define LIBAVUTIL_VERSION_MINOR 10 | |||||
#define LIBAVUTIL_VERSION_MICRO 2 | |||||
#define LIBAVUTIL_VERSION_MINOR 11 | |||||
#define LIBAVUTIL_VERSION_MICRO 0 | |||||
#define LIBAVUTIL_VERSION_INT AV_VERSION_INT(LIBAVUTIL_VERSION_MAJOR, \ | #define LIBAVUTIL_VERSION_INT AV_VERSION_INT(LIBAVUTIL_VERSION_MAJOR, \ | ||||
LIBAVUTIL_VERSION_MINOR, \ | LIBAVUTIL_VERSION_MINOR, \ | ||||
@@ -60,6 +60,8 @@ static const struct { | |||||
{ AV_CPU_FLAG_SSE4, "sse4.1" }, | { AV_CPU_FLAG_SSE4, "sse4.1" }, | ||||
{ AV_CPU_FLAG_SSE42, "sse4.2" }, | { AV_CPU_FLAG_SSE42, "sse4.2" }, | ||||
{ AV_CPU_FLAG_AVX, "avx" }, | { AV_CPU_FLAG_AVX, "avx" }, | ||||
{ AV_CPU_FLAG_XOP, "xop" }, | |||||
{ AV_CPU_FLAG_FMA4, "fma4" }, | |||||
{ AV_CPU_FLAG_3DNOW, "3dnow" }, | { AV_CPU_FLAG_3DNOW, "3dnow" }, | ||||
{ AV_CPU_FLAG_3DNOWEXT, "3dnowext" }, | { AV_CPU_FLAG_3DNOWEXT, "3dnowext" }, | ||||
#endif | #endif | ||||
@@ -38,6 +38,8 @@ | |||||
#define AV_CPU_FLAG_SSE4 0x0100 ///< Penryn SSE4.1 functions | #define AV_CPU_FLAG_SSE4 0x0100 ///< Penryn SSE4.1 functions | ||||
#define AV_CPU_FLAG_SSE42 0x0200 ///< Nehalem SSE4.2 functions | #define AV_CPU_FLAG_SSE42 0x0200 ///< Nehalem SSE4.2 functions | ||||
#define AV_CPU_FLAG_AVX 0x4000 ///< AVX functions: requires OS support even if YMM registers aren't used | #define AV_CPU_FLAG_AVX 0x4000 ///< AVX functions: requires OS support even if YMM registers aren't used | ||||
#define AV_CPU_FLAG_XOP 0x0400 ///< Bulldozer XOP functions | |||||
#define AV_CPU_FLAG_FMA4 0x0800 ///< Bulldozer FMA4 functions | |||||
#define AV_CPU_FLAG_IWMMXT 0x0100 ///< XScale IWMMXT | #define AV_CPU_FLAG_IWMMXT 0x0100 ///< XScale IWMMXT | ||||
#define AV_CPU_FLAG_ALTIVEC 0x0001 ///< standard | #define AV_CPU_FLAG_ALTIVEC 0x0001 ///< standard | ||||
@@ -133,6 +133,15 @@ int ff_get_cpu_flags_x86(void) | |||||
rval & AV_CPU_FLAG_SSE2 && !(ecx & 0x00000040)) { | rval & AV_CPU_FLAG_SSE2 && !(ecx & 0x00000040)) { | ||||
rval |= AV_CPU_FLAG_SSE2SLOW; | rval |= AV_CPU_FLAG_SSE2SLOW; | ||||
} | } | ||||
/* XOP and FMA4 use the AVX instruction coding scheme, so they can't be | |||||
* used unless the OS has AVX support. */ | |||||
if (rval & AV_CPU_FLAG_AVX) { | |||||
if (ecx & 0x00000800) | |||||
rval |= AV_CPU_FLAG_XOP; | |||||
if (ecx & 0x00010000) | |||||
rval |= AV_CPU_FLAG_FMA4; | |||||
} | |||||
} | } | ||||
if (!strncmp(vendor.c, "GenuineIntel", 12)) { | if (!strncmp(vendor.c, "GenuineIntel", 12)) { | ||||