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avcodec/mips: loongson optimize mmi load and store operators 

1.MMI_ load/store macros are defined in libavutil/mips/mmiutils.h
2.Replace some unnecessary unaligned access with aligned operator
3.The MMI_ load/store is compatible with cpu loongson2e/2f which not support instructions start with gs

Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
tags/n3.2
Zhou Xiaoyong Michael Niedermayer 8 years ago
parent
b9cd922660
commit
89ec4adad6
9 changed files with 2066 additions and 2306 deletions
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  1. +70
    -69
      libavcodec/mips/blockdsp_mmi.c
  2. +90
    -103
      libavcodec/mips/h264chroma_mmi.c
  3. +1017
    -1109
      libavcodec/mips/h264dsp_mmi.c
  4. +126
    -133
      libavcodec/mips/h264pred_mmi.c
  5. +324
    -453
      libavcodec/mips/h264qpel_mmi.c
  6. +241
    -308
      libavcodec/mips/hpeldsp_mmi.c
  7. +73
    -57
      libavcodec/mips/idctdsp_mmi.c
  8. +63
    -49
      libavcodec/mips/mpegvideo_mmi.c
  9. +62
    -25
      libavcodec/mips/pixblockdsp_mmi.c

+ 70
- 69
libavcodec/mips/blockdsp_mmi.c View File

@@ -22,11 +22,12 @@
*/ */


#include "blockdsp_mips.h" #include "blockdsp_mips.h"
#include "libavutil/mips/asmdefs.h"
#include "libavutil/mips/mmiutils.h"


void ff_fill_block16_mmi(uint8_t *block, uint8_t value, int line_size, int h) void ff_fill_block16_mmi(uint8_t *block, uint8_t value, int line_size, int h)
{ {
double ftmp[1]; double ftmp[1];
DECLARE_VAR_ALL64;


__asm__ volatile ( __asm__ volatile (
"mtc1 %[value], %[ftmp0] \n\t" "mtc1 %[value], %[ftmp0] \n\t"
@@ -34,15 +35,14 @@ void ff_fill_block16_mmi(uint8_t *block, uint8_t value, int line_size, int h)
"punpcklbh %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "punpcklbh %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"punpcklbh %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "punpcklbh %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"1: \n\t" "1: \n\t"
"gssdlc1 %[ftmp0], 0x07(%[block]) \n\t"
"gssdrc1 %[ftmp0], 0x00(%[block]) \n\t"
PTR_ADDI "%[h], %[h], -0x01 \n\t"
"gssdlc1 %[ftmp0], 0x0f(%[block]) \n\t"
"gssdrc1 %[ftmp0], 0x08(%[block]) \n\t"
MMI_SDC1(%[ftmp0], %[block], 0x00)
PTR_ADDI "%[h], %[h], -0x01 \n\t"
MMI_SDC1(%[ftmp0], %[block], 0x08)
PTR_ADDU "%[block], %[block], %[line_size] \n\t" PTR_ADDU "%[block], %[block], %[line_size] \n\t"
"bnez %[h], 1b \n\t" "bnez %[h], 1b \n\t"
: [block]"+&r"(block), [h]"+&r"(h),
[ftmp0]"=&f"(ftmp[0])
: [ftmp0]"=&f"(ftmp[0]),
RESTRICT_ASM_ALL64
[block]"+&r"(block), [h]"+&r"(h)
: [value]"r"(value), [line_size]"r"((mips_reg)line_size) : [value]"r"(value), [line_size]"r"((mips_reg)line_size)
: "memory" : "memory"
); );
@@ -51,6 +51,7 @@ void ff_fill_block16_mmi(uint8_t *block, uint8_t value, int line_size, int h)
void ff_fill_block8_mmi(uint8_t *block, uint8_t value, int line_size, int h) void ff_fill_block8_mmi(uint8_t *block, uint8_t value, int line_size, int h)
{ {
double ftmp0; double ftmp0;
DECLARE_VAR_ALL64;


__asm__ volatile ( __asm__ volatile (
"mtc1 %[value], %[ftmp0] \n\t" "mtc1 %[value], %[ftmp0] \n\t"
@@ -58,13 +59,13 @@ void ff_fill_block8_mmi(uint8_t *block, uint8_t value, int line_size, int h)
"punpcklbh %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "punpcklbh %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"punpcklbh %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "punpcklbh %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"1: \n\t" "1: \n\t"
"gssdlc1 %[ftmp0], 0x07(%[block]) \n\t"
"gssdrc1 %[ftmp0], 0x00(%[block]) \n\t"
MMI_SDC1(%[ftmp0], %[block], 0x00)
PTR_ADDI "%[h], %[h], -0x01 \n\t" PTR_ADDI "%[h], %[h], -0x01 \n\t"
PTR_ADDU "%[block], %[block], %[line_size] \n\t" PTR_ADDU "%[block], %[block], %[line_size] \n\t"
"bnez %[h], 1b \n\t" "bnez %[h], 1b \n\t"
: [block]"+&r"(block), [h]"+&r"(h),
[ftmp0]"=&f"(ftmp0)
: [ftmp0]"=&f"(ftmp0),
RESTRICT_ASM_ALL64
[block]"+&r"(block), [h]"+&r"(h)
: [value]"r"(value), [line_size]"r"((mips_reg)line_size) : [value]"r"(value), [line_size]"r"((mips_reg)line_size)
: "memory" : "memory"
); );
@@ -77,14 +78,14 @@ void ff_clear_block_mmi(int16_t *block)
__asm__ volatile ( __asm__ volatile (
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"xor %[ftmp1], %[ftmp1], %[ftmp1] \n\t" "xor %[ftmp1], %[ftmp1], %[ftmp1] \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x00(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x10(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x20(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x30(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x40(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x50(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x60(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x70(%[block]) \n\t"
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x00)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x10)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x20)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x30)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x40)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x50)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x60)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x70)
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]) : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1])
: [block]"r"(block) : [block]"r"(block)
: "memory" : "memory"
@@ -98,61 +99,61 @@ void ff_clear_blocks_mmi(int16_t *block)
__asm__ volatile ( __asm__ volatile (
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"xor %[ftmp1], %[ftmp1], %[ftmp1] \n\t" "xor %[ftmp1], %[ftmp1], %[ftmp1] \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x00(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x10(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x20(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x30(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x40(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x50(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x60(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x70(%[block]) \n\t"
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x00)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x10)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x20)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x30)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x40)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x50)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x60)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x70)


"gssqc1 %[ftmp0], %[ftmp1], 0x80(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x90(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0xa0(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0xb0(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0xc0(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0xd0(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0xe0(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0xf0(%[block]) \n\t"
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x80)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x90)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0xa0)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0xb0)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0xc0)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0xd0)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0xe0)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0xf0)


"gssqc1 %[ftmp0], %[ftmp1], 0x100(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x110(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x120(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x130(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x140(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x150(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x160(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x170(%[block]) \n\t"
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x100)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x110)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x120)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x130)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x140)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x150)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x160)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x170)


"gssqc1 %[ftmp0], %[ftmp1], 0x180(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x190(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x1a0(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x1b0(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x1c0(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x1d0(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x1e0(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x1f0(%[block]) \n\t"
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x180)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x190)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x1a0)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x1b0)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x1c0)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x1d0)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x1e0)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x1f0)


"gssqc1 %[ftmp0], %[ftmp1], 0x200(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x210(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x220(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x230(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x240(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x250(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x260(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x270(%[block]) \n\t"
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x200)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x210)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x220)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x230)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x240)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x250)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x260)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x270)


"gssqc1 %[ftmp0], %[ftmp1], 0x280(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x290(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x2a0(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x2b0(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x2c0(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x2d0(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x2e0(%[block]) \n\t"
"gssqc1 %[ftmp0], %[ftmp1], 0x2f0(%[block]) \n\t"
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x280)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x290)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x2a0)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x2b0)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x2c0)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x2d0)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x2e0)
MMI_SQC1(%[ftmp0], %[ftmp1], %[block], 0x2f0)
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]) : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1])
: [block]"r"((mips_reg)block)
: [block]"r"((uint64_t *)block)
: "memory" : "memory"
); );
} }

+ 90
- 103
libavcodec/mips/h264chroma_mmi.c View File

@@ -24,7 +24,7 @@


#include "h264chroma_mips.h" #include "h264chroma_mips.h"
#include "constants.h" #include "constants.h"
#include "libavutil/mips/asmdefs.h"
#include "libavutil/mips/mmiutils.h"


void ff_put_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride, void ff_put_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
int h, int x, int y) int h, int x, int y)
@@ -37,6 +37,7 @@ void ff_put_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
double ftmp[10]; double ftmp[10];
uint64_t tmp[1]; uint64_t tmp[1];
mips_reg addr[1]; mips_reg addr[1];
DECLARE_VAR_ALL64;


if (D) { if (D) {
__asm__ volatile ( __asm__ volatile (
@@ -47,16 +48,13 @@ void ff_put_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
"mtc1 %[tmp0], %[ftmp9] \n\t" "mtc1 %[tmp0], %[ftmp9] \n\t"
"pshufh %[C], %[C], %[ftmp0] \n\t" "pshufh %[C], %[C], %[ftmp0] \n\t"
"pshufh %[D], %[D], %[ftmp0] \n\t" "pshufh %[D], %[D], %[ftmp0] \n\t"

"1: \n\t" "1: \n\t"
PTR_ADDU "%[addr0], %[src], %[stride] \n\t" PTR_ADDU "%[addr0], %[src], %[stride] \n\t"
"gsldlc1 %[ftmp1], 0x07(%[src]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[src]) \n\t"
"gsldlc1 %[ftmp2], 0x08(%[src]) \n\t"
"gsldrc1 %[ftmp2], 0x01(%[src]) \n\t"
"gsldlc1 %[ftmp3], 0x07(%[addr0]) \n\t"
"gsldrc1 %[ftmp3], 0x00(%[addr0]) \n\t"
"gsldlc1 %[ftmp4], 0x08(%[addr0]) \n\t"
"gsldrc1 %[ftmp4], 0x01(%[addr0]) \n\t"
MMI_ULDC1(%[ftmp1], %[src], 0x00)
MMI_ULDC1(%[ftmp2], %[src], 0x01)
MMI_ULDC1(%[ftmp3], %[addr0], 0x00)
MMI_ULDC1(%[ftmp4], %[addr0], 0x01)


"punpcklbh %[ftmp5], %[ftmp1], %[ftmp0] \n\t" "punpcklbh %[ftmp5], %[ftmp1], %[ftmp0] \n\t"
"punpckhbh %[ftmp6], %[ftmp1], %[ftmp0] \n\t" "punpckhbh %[ftmp6], %[ftmp1], %[ftmp0] \n\t"
@@ -88,7 +86,7 @@ void ff_put_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
"psrlh %[ftmp2], %[ftmp2], %[ftmp9] \n\t" "psrlh %[ftmp2], %[ftmp2], %[ftmp9] \n\t"
"packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t" "packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
"addi %[h], %[h], -0x01 \n\t" "addi %[h], %[h], -0x01 \n\t"
"sdc1 %[ftmp1], 0x00(%[dst]) \n\t"
MMI_SDC1(%[ftmp1], %[dst], 0x00)
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
PTR_ADDU "%[dst], %[dst], %[stride] \n\t" PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
"bnez %[h], 1b \n\t" "bnez %[h], 1b \n\t"
@@ -98,6 +96,7 @@ void ff_put_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]), [ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
[ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]), [ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]),
[tmp0]"=&r"(tmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_ALL64
[addr0]"=&r"(addr[0]), [addr0]"=&r"(addr[0]),
[dst]"+&r"(dst), [src]"+&r"(src), [dst]"+&r"(dst), [src]"+&r"(src),
[h]"+&r"(h) [h]"+&r"(h)
@@ -115,12 +114,11 @@ void ff_put_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
"pshufh %[A], %[A], %[ftmp0] \n\t" "pshufh %[A], %[A], %[ftmp0] \n\t"
"pshufh %[E], %[E], %[ftmp0] \n\t" "pshufh %[E], %[E], %[ftmp0] \n\t"
"mtc1 %[tmp0], %[ftmp7] \n\t" "mtc1 %[tmp0], %[ftmp7] \n\t"

"1: \n\t" "1: \n\t"
PTR_ADDU "%[addr0], %[src], %[step] \n\t" PTR_ADDU "%[addr0], %[src], %[step] \n\t"
"gsldlc1 %[ftmp1], 0x07(%[src]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[src]) \n\t"
"gsldlc1 %[ftmp2], 0x07(%[addr0]) \n\t"
"gsldrc1 %[ftmp2], 0x00(%[addr0]) \n\t"
MMI_ULDC1(%[ftmp1], %[src], 0x00)
MMI_ULDC1(%[ftmp2], %[addr0], 0x00)


"punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t" "punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
"punpckhbh %[ftmp4], %[ftmp1], %[ftmp0] \n\t" "punpckhbh %[ftmp4], %[ftmp1], %[ftmp0] \n\t"
@@ -139,7 +137,7 @@ void ff_put_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
"psrlh %[ftmp2], %[ftmp2], %[ftmp7] \n\t" "psrlh %[ftmp2], %[ftmp2], %[ftmp7] \n\t"
"packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t" "packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
"addi %[h], %[h], -0x01 \n\t" "addi %[h], %[h], -0x01 \n\t"
"sdc1 %[ftmp1], 0x00(%[dst]) \n\t"
MMI_SDC1(%[ftmp1], %[dst], 0x00)
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
PTR_ADDU "%[dst], %[dst], %[stride] \n\t" PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
"bnez %[h], 1b \n\t" "bnez %[h], 1b \n\t"
@@ -148,6 +146,7 @@ void ff_put_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]), [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]), [ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
[tmp0]"=&r"(tmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_ALL64
[addr0]"=&r"(addr[0]), [addr0]"=&r"(addr[0]),
[dst]"+&r"(dst), [src]"+&r"(src), [dst]"+&r"(dst), [src]"+&r"(src),
[h]"+&r"(h) [h]"+&r"(h)
@@ -162,9 +161,9 @@ void ff_put_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
"dli %[tmp0], 0x06 \n\t" "dli %[tmp0], 0x06 \n\t"
"pshufh %[A], %[A], %[ftmp0] \n\t" "pshufh %[A], %[A], %[ftmp0] \n\t"
"mtc1 %[tmp0], %[ftmp4] \n\t" "mtc1 %[tmp0], %[ftmp4] \n\t"

"1: \n\t" "1: \n\t"
"gsldlc1 %[ftmp1], 0x07(%[src]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[src]) \n\t"
MMI_ULDC1(%[ftmp1], %[src], 0x00)
"punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t" "punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t"
"punpckhbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t" "punpckhbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
"pmullh %[ftmp1], %[ftmp2], %[A] \n\t" "pmullh %[ftmp1], %[ftmp2], %[A] \n\t"
@@ -175,11 +174,10 @@ void ff_put_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
"psrlh %[ftmp2], %[ftmp2], %[ftmp4] \n\t" "psrlh %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
"packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t" "packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"sdc1 %[ftmp1], 0x00(%[dst]) \n\t"
MMI_SDC1(%[ftmp1], %[dst], 0x00)


PTR_ADDU "%[dst], %[dst], %[stride] \n\t" PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
"gsldlc1 %[ftmp1], 0x07(%[src]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[src]) \n\t"
MMI_ULDC1(%[ftmp1], %[src], 0x00)
"punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t" "punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t"
"punpckhbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t" "punpckhbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
"pmullh %[ftmp1], %[ftmp2], %[A] \n\t" "pmullh %[ftmp1], %[ftmp2], %[A] \n\t"
@@ -190,7 +188,7 @@ void ff_put_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
"psrlh %[ftmp2], %[ftmp2], %[ftmp4] \n\t" "psrlh %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
"packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t" "packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
"addi %[h], %[h], -0x02 \n\t" "addi %[h], %[h], -0x02 \n\t"
"sdc1 %[ftmp1], 0x00(%[dst]) \n\t"
MMI_SDC1(%[ftmp1], %[dst], 0x00)


PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
PTR_ADDU "%[dst], %[dst], %[stride] \n\t" PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
@@ -199,6 +197,7 @@ void ff_put_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
[ftmp4]"=&f"(ftmp[4]), [ftmp4]"=&f"(ftmp[4]),
[tmp0]"=&r"(tmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_ALL64
[dst]"+&r"(dst), [src]"+&r"(src), [dst]"+&r"(dst), [src]"+&r"(src),
[h]"+&r"(h) [h]"+&r"(h)
: [stride]"r"((mips_reg)stride),[ff_pw_32]"f"(ff_pw_32), : [stride]"r"((mips_reg)stride),[ff_pw_32]"f"(ff_pw_32),
@@ -219,6 +218,7 @@ void ff_avg_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
double ftmp[10]; double ftmp[10];
uint64_t tmp[1]; uint64_t tmp[1];
mips_reg addr[1]; mips_reg addr[1];
DECLARE_VAR_ALL64;


if (D) { if (D) {
__asm__ volatile ( __asm__ volatile (
@@ -229,16 +229,13 @@ void ff_avg_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
"mtc1 %[tmp0], %[ftmp9] \n\t" "mtc1 %[tmp0], %[ftmp9] \n\t"
"pshufh %[C], %[C], %[ftmp0] \n\t" "pshufh %[C], %[C], %[ftmp0] \n\t"
"pshufh %[D], %[D], %[ftmp0] \n\t" "pshufh %[D], %[D], %[ftmp0] \n\t"

"1: \n\t" "1: \n\t"
PTR_ADDU "%[addr0], %[src], %[stride] \n\t" PTR_ADDU "%[addr0], %[src], %[stride] \n\t"
"gsldlc1 %[ftmp1], 0x07(%[src]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[src]) \n\t"
"gsldlc1 %[ftmp2], 0x08(%[src]) \n\t"
"gsldrc1 %[ftmp2], 0x01(%[src]) \n\t"
"gsldlc1 %[ftmp3], 0x07(%[addr0]) \n\t"
"gsldrc1 %[ftmp3], 0x00(%[addr0]) \n\t"
"gsldlc1 %[ftmp4], 0x08(%[addr0]) \n\t"
"gsldrc1 %[ftmp4], 0x01(%[addr0]) \n\t"
MMI_ULDC1(%[ftmp1], %[src], 0x00)
MMI_ULDC1(%[ftmp2], %[src], 0x01)
MMI_ULDC1(%[ftmp3], %[addr0], 0x00)
MMI_ULDC1(%[ftmp4], %[addr0], 0x01)


"punpcklbh %[ftmp5], %[ftmp1], %[ftmp0] \n\t" "punpcklbh %[ftmp5], %[ftmp1], %[ftmp0] \n\t"
"punpckhbh %[ftmp6], %[ftmp1], %[ftmp0] \n\t" "punpckhbh %[ftmp6], %[ftmp1], %[ftmp0] \n\t"
@@ -269,10 +266,10 @@ void ff_avg_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
"psrlh %[ftmp1], %[ftmp1], %[ftmp9] \n\t" "psrlh %[ftmp1], %[ftmp1], %[ftmp9] \n\t"
"psrlh %[ftmp2], %[ftmp2], %[ftmp9] \n\t" "psrlh %[ftmp2], %[ftmp2], %[ftmp9] \n\t"
"packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t" "packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
"ldc1 %[ftmp2], 0x00(%[dst]) \n\t"
MMI_LDC1(%[ftmp2], %[dst], 0x00)
"pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
"addi %[h], %[h], -0x01 \n\t" "addi %[h], %[h], -0x01 \n\t"
"sdc1 %[ftmp1], 0x00(%[dst]) \n\t"
MMI_SDC1(%[ftmp1], %[dst], 0x00)
PTR_ADDU "%[dst], %[dst], %[stride] \n\t" PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"bnez %[h], 1b \n\t" "bnez %[h], 1b \n\t"
@@ -282,6 +279,7 @@ void ff_avg_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]), [ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
[ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]), [ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]),
[tmp0]"=&r"(tmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_ALL64
[addr0]"=&r"(addr[0]), [addr0]"=&r"(addr[0]),
[dst]"+&r"(dst), [src]"+&r"(src), [dst]"+&r"(dst), [src]"+&r"(src),
[h]"+&r"(h) [h]"+&r"(h)
@@ -299,12 +297,11 @@ void ff_avg_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
"pshufh %[A], %[A], %[ftmp0] \n\t" "pshufh %[A], %[A], %[ftmp0] \n\t"
"pshufh %[E], %[E], %[ftmp0] \n\t" "pshufh %[E], %[E], %[ftmp0] \n\t"
"mtc1 %[tmp0], %[ftmp7] \n\t" "mtc1 %[tmp0], %[ftmp7] \n\t"

"1: \n\t" "1: \n\t"
PTR_ADDU "%[addr0], %[src], %[step] \n\t" PTR_ADDU "%[addr0], %[src], %[step] \n\t"
"gsldlc1 %[ftmp1], 0x07(%[src]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[src]) \n\t"
"gsldlc1 %[ftmp2], 0x07(%[addr0]) \n\t"
"gsldrc1 %[ftmp2], 0x00(%[addr0]) \n\t"
MMI_ULDC1(%[ftmp1], %[src], 0x00)
MMI_ULDC1(%[ftmp2], %[addr0], 0x00)


"punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t" "punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
"punpckhbh %[ftmp4], %[ftmp1], %[ftmp0] \n\t" "punpckhbh %[ftmp4], %[ftmp1], %[ftmp0] \n\t"
@@ -322,10 +319,10 @@ void ff_avg_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
"psrlh %[ftmp1], %[ftmp1], %[ftmp7] \n\t" "psrlh %[ftmp1], %[ftmp1], %[ftmp7] \n\t"
"psrlh %[ftmp2], %[ftmp2], %[ftmp7] \n\t" "psrlh %[ftmp2], %[ftmp2], %[ftmp7] \n\t"
"packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t" "packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
"ldc1 %[ftmp2], 0x00(%[dst]) \n\t"
MMI_LDC1(%[ftmp2], %[dst], 0x00)
"pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
"addi %[h], %[h], -0x01 \n\t" "addi %[h], %[h], -0x01 \n\t"
"sdc1 %[ftmp1], 0x00(%[dst]) \n\t"
MMI_SDC1(%[ftmp1], %[dst], 0x00)
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
PTR_ADDU "%[dst], %[dst], %[stride] \n\t" PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
"bnez %[h], 1b \n\t" "bnez %[h], 1b \n\t"
@@ -334,6 +331,7 @@ void ff_avg_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]), [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]), [ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
[tmp0]"=&r"(tmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_ALL64
[addr0]"=&r"(addr[0]), [addr0]"=&r"(addr[0]),
[dst]"+&r"(dst), [src]"+&r"(src), [dst]"+&r"(dst), [src]"+&r"(src),
[h]"+&r"(h) [h]"+&r"(h)
@@ -348,9 +346,9 @@ void ff_avg_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
"dli %[tmp0], 0x06 \n\t" "dli %[tmp0], 0x06 \n\t"
"pshufh %[A], %[A], %[ftmp0] \n\t" "pshufh %[A], %[A], %[ftmp0] \n\t"
"mtc1 %[tmp0], %[ftmp4] \n\t" "mtc1 %[tmp0], %[ftmp4] \n\t"

"1: \n\t" "1: \n\t"
"gsldlc1 %[ftmp1], 0x07(%[src]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[src]) \n\t"
MMI_ULDC1(%[ftmp1], %[src], 0x00)
"punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t" "punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t"
"punpckhbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t" "punpckhbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
"pmullh %[ftmp1], %[ftmp2], %[A] \n\t" "pmullh %[ftmp1], %[ftmp2], %[A] \n\t"
@@ -360,14 +358,13 @@ void ff_avg_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
"psrlh %[ftmp1], %[ftmp1], %[ftmp4] \n\t" "psrlh %[ftmp1], %[ftmp1], %[ftmp4] \n\t"
"psrlh %[ftmp2], %[ftmp2], %[ftmp4] \n\t" "psrlh %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
"packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t" "packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
"ldc1 %[ftmp2], 0x00(%[dst]) \n\t"
MMI_LDC1(%[ftmp2], %[dst], 0x00)
"pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"sdc1 %[ftmp1], 0x00(%[dst]) \n\t"
MMI_SDC1(%[ftmp1], %[dst], 0x00)
PTR_ADDU "%[dst], %[dst], %[stride] \n\t" PTR_ADDU "%[dst], %[dst], %[stride] \n\t"


"gsldlc1 %[ftmp1], 0x07(%[src]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[src]) \n\t"
MMI_ULDC1(%[ftmp1], %[src], 0x00)
"punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t" "punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t"
"punpckhbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t" "punpckhbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
"pmullh %[ftmp1], %[ftmp2], %[A] \n\t" "pmullh %[ftmp1], %[ftmp2], %[A] \n\t"
@@ -377,10 +374,10 @@ void ff_avg_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
"psrlh %[ftmp1], %[ftmp1], %[ftmp4] \n\t" "psrlh %[ftmp1], %[ftmp1], %[ftmp4] \n\t"
"psrlh %[ftmp2], %[ftmp2], %[ftmp4] \n\t" "psrlh %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
"packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t" "packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
"ldc1 %[ftmp2], 0x00(%[dst]) \n\t"
MMI_LDC1(%[ftmp2], %[dst], 0x00)
"pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
"addi %[h], %[h], -0x02 \n\t" "addi %[h], %[h], -0x02 \n\t"
"sdc1 %[ftmp1], 0x00(%[dst]) \n\t"
MMI_SDC1(%[ftmp1], %[dst], 0x00)


PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
PTR_ADDU "%[dst], %[dst], %[stride] \n\t" PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
@@ -389,6 +386,7 @@ void ff_avg_h264_chroma_mc8_mmi(uint8_t *dst, uint8_t *src, int stride,
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
[ftmp4]"=&f"(ftmp[4]), [ftmp4]"=&f"(ftmp[4]),
[tmp0]"=&r"(tmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_ALL64
[dst]"+&r"(dst), [src]"+&r"(src), [dst]"+&r"(dst), [src]"+&r"(src),
[h]"+&r"(h) [h]"+&r"(h)
: [stride]"r"((mips_reg)stride),[ff_pw_32]"f"(ff_pw_32), : [stride]"r"((mips_reg)stride),[ff_pw_32]"f"(ff_pw_32),
@@ -409,7 +407,7 @@ void ff_put_h264_chroma_mc4_mmi(uint8_t *dst, uint8_t *src, int stride,
double ftmp[8]; double ftmp[8];
uint64_t tmp[1]; uint64_t tmp[1];
mips_reg addr[1]; mips_reg addr[1];
uint64_t low32;
DECLARE_VAR_LOW32;


if (D) { if (D) {
__asm__ volatile ( __asm__ volatile (
@@ -420,16 +418,13 @@ void ff_put_h264_chroma_mc4_mmi(uint8_t *dst, uint8_t *src, int stride,
"mtc1 %[tmp0], %[ftmp7] \n\t" "mtc1 %[tmp0], %[ftmp7] \n\t"
"pshufh %[C], %[C], %[ftmp0] \n\t" "pshufh %[C], %[C], %[ftmp0] \n\t"
"pshufh %[D], %[D], %[ftmp0] \n\t" "pshufh %[D], %[D], %[ftmp0] \n\t"

"1: \n\t" "1: \n\t"
PTR_ADDU "%[addr0], %[src], %[stride] \n\t" PTR_ADDU "%[addr0], %[src], %[stride] \n\t"
"uld %[low32], 0x00(%[src]) \n\t"
"mtc1 %[low32], %[ftmp1] \n\t"
"uld %[low32], 0x01(%[src]) \n\t"
"mtc1 %[low32], %[ftmp2] \n\t"
"uld %[low32], 0x00(%[addr0]) \n\t"
"mtc1 %[low32], %[ftmp3] \n\t"
"uld %[low32], 0x01(%[addr0]) \n\t"
"mtc1 %[low32], %[ftmp4] \n\t"
MMI_ULWC1(%[ftmp1], %[src], 0x00)
MMI_ULWC1(%[ftmp2], %[src], 0x01)
MMI_ULWC1(%[ftmp3], %[addr0], 0x00)
MMI_ULWC1(%[ftmp4], %[addr0], 0x01)


"punpcklbh %[ftmp5], %[ftmp1], %[ftmp0] \n\t" "punpcklbh %[ftmp5], %[ftmp1], %[ftmp0] \n\t"
"punpcklbh %[ftmp6], %[ftmp2], %[ftmp0] \n\t" "punpcklbh %[ftmp6], %[ftmp2], %[ftmp0] \n\t"
@@ -448,7 +443,7 @@ void ff_put_h264_chroma_mc4_mmi(uint8_t *dst, uint8_t *src, int stride,
"psrlh %[ftmp1], %[ftmp1], %[ftmp7] \n\t" "psrlh %[ftmp1], %[ftmp1], %[ftmp7] \n\t"
"packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t" "packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
"addi %[h], %[h], -0x01 \n\t" "addi %[h], %[h], -0x01 \n\t"
"swc1 %[ftmp1], 0x00(%[dst]) \n\t"
MMI_SWC1(%[ftmp1], %[dst], 0x00)
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
PTR_ADDU "%[dst], %[dst], %[stride] \n\t" PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
"bnez %[h], 1b \n\t" "bnez %[h], 1b \n\t"
@@ -457,10 +452,10 @@ void ff_put_h264_chroma_mc4_mmi(uint8_t *dst, uint8_t *src, int stride,
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]), [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]), [ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
[tmp0]"=&r"(tmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_LOW32
[addr0]"=&r"(addr[0]), [addr0]"=&r"(addr[0]),
[dst]"+&r"(dst), [src]"+&r"(src), [dst]"+&r"(dst), [src]"+&r"(src),
[h]"+&r"(h),
[low32]"=&r"(low32)
[h]"+&r"(h)
: [stride]"r"((mips_reg)stride),[ff_pw_32]"f"(ff_pw_32), : [stride]"r"((mips_reg)stride),[ff_pw_32]"f"(ff_pw_32),
[A]"f"(A), [B]"f"(B), [A]"f"(A), [B]"f"(B),
[C]"f"(C), [D]"f"(D) [C]"f"(C), [D]"f"(D)
@@ -475,12 +470,11 @@ void ff_put_h264_chroma_mc4_mmi(uint8_t *dst, uint8_t *src, int stride,
"pshufh %[A], %[A], %[ftmp0] \n\t" "pshufh %[A], %[A], %[ftmp0] \n\t"
"pshufh %[E], %[E], %[ftmp0] \n\t" "pshufh %[E], %[E], %[ftmp0] \n\t"
"mtc1 %[tmp0], %[ftmp5] \n\t" "mtc1 %[tmp0], %[ftmp5] \n\t"

"1: \n\t" "1: \n\t"
PTR_ADDU "%[addr0], %[src], %[step] \n\t" PTR_ADDU "%[addr0], %[src], %[step] \n\t"
"uld %[low32], 0x00(%[src]) \n\t"
"mtc1 %[low32], %[ftmp1] \n\t"
"uld %[low32], 0x00(%[addr0]) \n\t"
"mtc1 %[low32], %[ftmp2] \n\t"
MMI_ULWC1(%[ftmp1], %[src], 0x00)
MMI_ULWC1(%[ftmp2], %[addr0], 0x00)


"punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t" "punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
"punpcklbh %[ftmp4], %[ftmp2], %[ftmp0] \n\t" "punpcklbh %[ftmp4], %[ftmp2], %[ftmp0] \n\t"
@@ -492,7 +486,7 @@ void ff_put_h264_chroma_mc4_mmi(uint8_t *dst, uint8_t *src, int stride,
"psrlh %[ftmp1], %[ftmp1], %[ftmp5] \n\t" "psrlh %[ftmp1], %[ftmp1], %[ftmp5] \n\t"
"packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t" "packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
"addi %[h], %[h], -0x01 \n\t" "addi %[h], %[h], -0x01 \n\t"
"swc1 %[ftmp1], 0x00(%[dst]) \n\t"
MMI_SWC1(%[ftmp1], %[dst], 0x00)
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
PTR_ADDU "%[dst], %[dst], %[stride] \n\t" PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
"bnez %[h], 1b \n\t" "bnez %[h], 1b \n\t"
@@ -500,10 +494,10 @@ void ff_put_h264_chroma_mc4_mmi(uint8_t *dst, uint8_t *src, int stride,
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]), [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
[tmp0]"=&r"(tmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_LOW32
[addr0]"=&r"(addr[0]), [addr0]"=&r"(addr[0]),
[dst]"+&r"(dst), [src]"+&r"(src), [dst]"+&r"(dst), [src]"+&r"(src),
[h]"+&r"(h),
[low32]"=&r"(low32)
[h]"+&r"(h)
: [stride]"r"((mips_reg)stride),[step]"r"((mips_reg)step), : [stride]"r"((mips_reg)stride),[step]"r"((mips_reg)step),
[ff_pw_32]"f"(ff_pw_32), [ff_pw_32]"f"(ff_pw_32),
[A]"f"(A), [E]"f"(E) [A]"f"(A), [E]"f"(E)
@@ -515,27 +509,26 @@ void ff_put_h264_chroma_mc4_mmi(uint8_t *dst, uint8_t *src, int stride,
"dli %[tmp0], 0x06 \n\t" "dli %[tmp0], 0x06 \n\t"
"pshufh %[A], %[A], %[ftmp0] \n\t" "pshufh %[A], %[A], %[ftmp0] \n\t"
"mtc1 %[tmp0], %[ftmp3] \n\t" "mtc1 %[tmp0], %[ftmp3] \n\t"

"1: \n\t" "1: \n\t"
"uld %[low32], 0x00(%[src]) \n\t"
"mtc1 %[low32], %[ftmp1] \n\t"
MMI_ULWC1(%[ftmp1], %[src], 0x00)
"punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t" "punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t"
"pmullh %[ftmp1], %[ftmp2], %[A] \n\t" "pmullh %[ftmp1], %[ftmp2], %[A] \n\t"
"paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t" "paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t"
"psrlh %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "psrlh %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
"packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t" "packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"swc1 %[ftmp1], 0x00(%[dst]) \n\t"
MMI_SWC1(%[ftmp1], %[dst], 0x00)
PTR_ADDU "%[dst], %[dst], %[stride] \n\t" PTR_ADDU "%[dst], %[dst], %[stride] \n\t"


"uld %[low32], 0x00(%[src]) \n\t"
"mtc1 %[low32], %[ftmp1] \n\t"
MMI_ULWC1(%[ftmp1], %[src], 0x00)
"punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t" "punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t"
"pmullh %[ftmp1], %[ftmp2], %[A] \n\t" "pmullh %[ftmp1], %[ftmp2], %[A] \n\t"
"paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t" "paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t"
"psrlh %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "psrlh %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
"packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t" "packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
"addi %[h], %[h], -0x02 \n\t" "addi %[h], %[h], -0x02 \n\t"
"swc1 %[ftmp1], 0x00(%[dst]) \n\t"
MMI_SWC1(%[ftmp1], %[dst], 0x00)


PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
PTR_ADDU "%[dst], %[dst], %[stride] \n\t" PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
@@ -543,9 +536,9 @@ void ff_put_h264_chroma_mc4_mmi(uint8_t *dst, uint8_t *src, int stride,
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
[tmp0]"=&r"(tmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_LOW32
[dst]"+&r"(dst), [src]"+&r"(src), [dst]"+&r"(dst), [src]"+&r"(src),
[h]"+&r"(h),
[low32]"=&r"(low32)
[h]"+&r"(h)
: [stride]"r"((mips_reg)stride),[ff_pw_32]"f"(ff_pw_32), : [stride]"r"((mips_reg)stride),[ff_pw_32]"f"(ff_pw_32),
[A]"f"(A) [A]"f"(A)
: "memory" : "memory"
@@ -564,7 +557,7 @@ void ff_avg_h264_chroma_mc4_mmi(uint8_t *dst, uint8_t *src, int stride,
double ftmp[8]; double ftmp[8];
uint64_t tmp[1]; uint64_t tmp[1];
mips_reg addr[1]; mips_reg addr[1];
uint64_t low32;
DECLARE_VAR_LOW32;


if (D) { if (D) {
__asm__ volatile ( __asm__ volatile (
@@ -575,16 +568,13 @@ void ff_avg_h264_chroma_mc4_mmi(uint8_t *dst, uint8_t *src, int stride,
"mtc1 %[tmp0], %[ftmp7] \n\t" "mtc1 %[tmp0], %[ftmp7] \n\t"
"pshufh %[C], %[C], %[ftmp0] \n\t" "pshufh %[C], %[C], %[ftmp0] \n\t"
"pshufh %[D], %[D], %[ftmp0] \n\t" "pshufh %[D], %[D], %[ftmp0] \n\t"

"1: \n\t" "1: \n\t"
PTR_ADDU "%[addr0], %[src], %[stride] \n\t" PTR_ADDU "%[addr0], %[src], %[stride] \n\t"
"uld %[low32], 0x00(%[src]) \n\t"
"mtc1 %[low32], %[ftmp1] \n\t"
"uld %[low32], 0x01(%[src]) \n\t"
"mtc1 %[low32], %[ftmp2] \n\t"
"uld %[low32], 0x00(%[addr0]) \n\t"
"mtc1 %[low32], %[ftmp3] \n\t"
"uld %[low32], 0x01(%[addr0]) \n\t"
"mtc1 %[low32], %[ftmp4] \n\t"
MMI_ULWC1(%[ftmp1], %[src], 0x00)
MMI_ULWC1(%[ftmp2], %[src], 0x01)
MMI_ULWC1(%[ftmp3], %[addr0], 0x00)
MMI_ULWC1(%[ftmp4], %[addr0], 0x01)


"punpcklbh %[ftmp5], %[ftmp1], %[ftmp0] \n\t" "punpcklbh %[ftmp5], %[ftmp1], %[ftmp0] \n\t"
"punpcklbh %[ftmp6], %[ftmp2], %[ftmp0] \n\t" "punpcklbh %[ftmp6], %[ftmp2], %[ftmp0] \n\t"
@@ -602,10 +592,10 @@ void ff_avg_h264_chroma_mc4_mmi(uint8_t *dst, uint8_t *src, int stride,
"paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t" "paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t"
"psrlh %[ftmp1], %[ftmp1], %[ftmp7] \n\t" "psrlh %[ftmp1], %[ftmp1], %[ftmp7] \n\t"
"packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t" "packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
"lwc1 %[ftmp2], 0x00(%[dst]) \n\t"
MMI_LWC1(%[ftmp2], %[dst], 0x00)
"pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
"addi %[h], %[h], -0x01 \n\t" "addi %[h], %[h], -0x01 \n\t"
"swc1 %[ftmp1], 0x00(%[dst]) \n\t"
MMI_SWC1(%[ftmp1], %[dst], 0x00)
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
PTR_ADDU "%[dst], %[dst], %[stride] \n\t" PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
"bnez %[h], 1b \n\t" "bnez %[h], 1b \n\t"
@@ -614,10 +604,10 @@ void ff_avg_h264_chroma_mc4_mmi(uint8_t *dst, uint8_t *src, int stride,
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]), [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]), [ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
[tmp0]"=&r"(tmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_LOW32
[addr0]"=&r"(addr[0]), [addr0]"=&r"(addr[0]),
[dst]"+&r"(dst), [src]"+&r"(src), [dst]"+&r"(dst), [src]"+&r"(src),
[h]"+&r"(h),
[low32]"=&r"(low32)
[h]"+&r"(h)
: [stride]"r"((mips_reg)stride),[ff_pw_32]"f"(ff_pw_32), : [stride]"r"((mips_reg)stride),[ff_pw_32]"f"(ff_pw_32),
[A]"f"(A), [B]"f"(B), [A]"f"(A), [B]"f"(B),
[C]"f"(C), [D]"f"(D) [C]"f"(C), [D]"f"(D)
@@ -634,10 +624,8 @@ void ff_avg_h264_chroma_mc4_mmi(uint8_t *dst, uint8_t *src, int stride,
"mtc1 %[tmp0], %[ftmp5] \n\t" "mtc1 %[tmp0], %[ftmp5] \n\t"
"1: \n\t" "1: \n\t"
PTR_ADDU "%[addr0], %[src], %[step] \n\t" PTR_ADDU "%[addr0], %[src], %[step] \n\t"
"uld %[low32], 0x00(%[src]) \n\t"
"mtc1 %[low32], %[ftmp1] \n\t"
"uld %[low32], 0x00(%[addr0]) \n\t"
"mtc1 %[low32], %[ftmp2] \n\t"
MMI_ULWC1(%[ftmp1], %[src], 0x00)
MMI_ULWC1(%[ftmp2], %[addr0], 0x00)


"punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t" "punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
"punpcklbh %[ftmp4], %[ftmp2], %[ftmp0] \n\t" "punpcklbh %[ftmp4], %[ftmp2], %[ftmp0] \n\t"
@@ -648,10 +636,10 @@ void ff_avg_h264_chroma_mc4_mmi(uint8_t *dst, uint8_t *src, int stride,
"paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t" "paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t"
"psrlh %[ftmp1], %[ftmp1], %[ftmp5] \n\t" "psrlh %[ftmp1], %[ftmp1], %[ftmp5] \n\t"
"packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t" "packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
"lwc1 %[ftmp2], 0x00(%[dst]) \n\t"
MMI_LWC1(%[ftmp2], %[dst], 0x00)
"pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
"addi %[h], %[h], -0x01 \n\t" "addi %[h], %[h], -0x01 \n\t"
"swc1 %[ftmp1], 0x00(%[dst]) \n\t"
MMI_SWC1(%[ftmp1], %[dst], 0x00)
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
PTR_ADDU "%[dst], %[dst], %[stride] \n\t" PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
"bnez %[h], 1b \n\t" "bnez %[h], 1b \n\t"
@@ -659,10 +647,10 @@ void ff_avg_h264_chroma_mc4_mmi(uint8_t *dst, uint8_t *src, int stride,
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]), [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
[tmp0]"=&r"(tmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_LOW32
[addr0]"=&r"(addr[0]), [addr0]"=&r"(addr[0]),
[dst]"+&r"(dst), [src]"+&r"(src), [dst]"+&r"(dst), [src]"+&r"(src),
[h]"+&r"(h),
[low32]"=&r"(low32)
[h]"+&r"(h)
: [stride]"r"((mips_reg)stride),[step]"r"((mips_reg)step), : [stride]"r"((mips_reg)stride),[step]"r"((mips_reg)step),
[ff_pw_32]"f"(ff_pw_32), [ff_pw_32]"f"(ff_pw_32),
[A]"f"(A), [E]"f"(E) [A]"f"(A), [E]"f"(E)
@@ -674,31 +662,30 @@ void ff_avg_h264_chroma_mc4_mmi(uint8_t *dst, uint8_t *src, int stride,
"dli %[tmp0], 0x06 \n\t" "dli %[tmp0], 0x06 \n\t"
"pshufh %[A], %[A], %[ftmp0] \n\t" "pshufh %[A], %[A], %[ftmp0] \n\t"
"mtc1 %[tmp0], %[ftmp3] \n\t" "mtc1 %[tmp0], %[ftmp3] \n\t"

"1: \n\t" "1: \n\t"
"uld %[low32], 0x00(%[src]) \n\t"
"mtc1 %[low32], %[ftmp1] \n\t"
MMI_ULWC1(%[ftmp1], %[src], 0x00)
"punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t" "punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t"
"pmullh %[ftmp1], %[ftmp2], %[A] \n\t" "pmullh %[ftmp1], %[ftmp2], %[A] \n\t"
"paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t" "paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t"
"psrlh %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "psrlh %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
"packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t" "packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
"lwc1 %[ftmp2], 0x00(%[dst]) \n\t"
MMI_LWC1(%[ftmp2], %[dst], 0x00)
"pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"swc1 %[ftmp1], 0x00(%[dst]) \n\t"
MMI_SWC1(%[ftmp1], %[dst], 0x00)
PTR_ADDU "%[dst], %[dst], %[stride] \n\t" PTR_ADDU "%[dst], %[dst], %[stride] \n\t"


"uld %[low32], 0x00(%[src]) \n\t"
"mtc1 %[low32], %[ftmp1] \n\t"
MMI_ULWC1(%[ftmp1], %[src], 0x00)
"punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t" "punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t"
"pmullh %[ftmp1], %[ftmp2], %[A] \n\t" "pmullh %[ftmp1], %[ftmp2], %[A] \n\t"
"paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t" "paddh %[ftmp1], %[ftmp1], %[ff_pw_32] \n\t"
"psrlh %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "psrlh %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
"packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t" "packushb %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
"lwc1 %[ftmp2], 0x00(%[dst]) \n\t"
MMI_LWC1(%[ftmp2], %[dst], 0x00)
"pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
"addi %[h], %[h], -0x02 \n\t" "addi %[h], %[h], -0x02 \n\t"
"swc1 %[ftmp1], 0x00(%[dst]) \n\t"
MMI_SWC1(%[ftmp1], %[dst], 0x00)


PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
PTR_ADDU "%[dst], %[dst], %[stride] \n\t" PTR_ADDU "%[dst], %[dst], %[stride] \n\t"
@@ -706,9 +693,9 @@ void ff_avg_h264_chroma_mc4_mmi(uint8_t *dst, uint8_t *src, int stride,
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
[tmp0]"=&r"(tmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_LOW32
[dst]"+&r"(dst), [src]"+&r"(src), [dst]"+&r"(dst), [src]"+&r"(src),
[h]"+&r"(h),
[low32]"=&r"(low32)
[h]"+&r"(h)
: [stride]"r"((mips_reg)stride),[ff_pw_32]"f"(ff_pw_32), : [stride]"r"((mips_reg)stride),[ff_pw_32]"f"(ff_pw_32),
[A]"f"(A) [A]"f"(A)
: "memory" : "memory"


+ 1017
- 1109
libavcodec/mips/h264dsp_mmi.c
File diff suppressed because it is too large
View File


+ 126
- 133
libavcodec/mips/h264pred_mmi.c View File

@@ -24,35 +24,33 @@


#include "h264pred_mips.h" #include "h264pred_mips.h"
#include "libavcodec/bit_depth_template.c" #include "libavcodec/bit_depth_template.c"
#include "libavutil/mips/asmdefs.h"
#include "libavutil/mips/mmiutils.h"
#include "constants.h" #include "constants.h"


void ff_pred16x16_vertical_8_mmi(uint8_t *src, ptrdiff_t stride) void ff_pred16x16_vertical_8_mmi(uint8_t *src, ptrdiff_t stride)
{ {
double ftmp[2]; double ftmp[2];
uint64_t tmp[1]; uint64_t tmp[1];
DECLARE_VAR_ALL64;


__asm__ volatile ( __asm__ volatile (
"dli %[tmp0], 0x08 \n\t" "dli %[tmp0], 0x08 \n\t"
"gsldlc1 %[ftmp0], 0x07(%[srcA]) \n\t"
"gsldrc1 %[ftmp0], 0x00(%[srcA]) \n\t"
"gsldlc1 %[ftmp1], 0x0f(%[srcA]) \n\t"
"gsldrc1 %[ftmp1], 0x08(%[srcA]) \n\t"
MMI_LDC1(%[ftmp0], %[srcA], 0x00)
MMI_LDC1(%[ftmp1], %[srcA], 0x08)

"1: \n\t" "1: \n\t"
"gssdlc1 %[ftmp0], 0x07(%[src]) \n\t"
"gssdrc1 %[ftmp0], 0x00(%[src]) \n\t"
"gssdlc1 %[ftmp1], 0x0f(%[src]) \n\t"
"gssdrc1 %[ftmp1], 0x08(%[src]) \n\t"
MMI_SDC1(%[ftmp0], %[src], 0x00)
MMI_SDC1(%[ftmp1], %[src], 0x08)
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"gssdlc1 %[ftmp0], 0x07(%[src]) \n\t"
"gssdrc1 %[ftmp0], 0x00(%[src]) \n\t"
"gssdlc1 %[ftmp1], 0x0f(%[src]) \n\t"
"gssdrc1 %[ftmp1], 0x08(%[src]) \n\t"
MMI_SDC1(%[ftmp0], %[src], 0x00)
MMI_SDC1(%[ftmp1], %[src], 0x08)

"daddi %[tmp0], %[tmp0], -0x01 \n\t" "daddi %[tmp0], %[tmp0], -0x01 \n\t"
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"bnez %[tmp0], 1b \n\t" "bnez %[tmp0], 1b \n\t"
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
[tmp0]"=&r"(tmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_ALL64
[src]"+&r"(src) [src]"+&r"(src)
: [stride]"r"((mips_reg)stride), [srcA]"r"((mips_reg)(src-stride)) : [stride]"r"((mips_reg)stride), [srcA]"r"((mips_reg)(src-stride))
: "memory" : "memory"
@@ -160,15 +158,14 @@ void ff_pred8x8l_top_dc_8_mmi(uint8_t *src, int has_topleft,
uint32_t dc; uint32_t dc;
double ftmp[11]; double ftmp[11];
mips_reg tmp[3]; mips_reg tmp[3];
DECLARE_VAR_ALL64;
DECLARE_VAR_ADDRT;


__asm__ volatile ( __asm__ volatile (
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"gsldlc1 %[ftmp10], 0x07(%[srcA]) \n\t"
"gsldrc1 %[ftmp10], 0x00(%[srcA]) \n\t"
"gsldlc1 %[ftmp9], 0x07(%[src0]) \n\t"
"gsldrc1 %[ftmp9], 0x00(%[src0]) \n\t"
"gsldlc1 %[ftmp8], 0x07(%[src1]) \n\t"
"gsldrc1 %[ftmp8], 0x00(%[src1]) \n\t"
MMI_ULDC1(%[ftmp10], %[srcA], 0x00)
MMI_ULDC1(%[ftmp9], %[src0], 0x00)
MMI_ULDC1(%[ftmp8], %[src1], 0x00)


"punpcklbh %[ftmp7], %[ftmp10], %[ftmp0] \n\t" "punpcklbh %[ftmp7], %[ftmp10], %[ftmp0] \n\t"
"punpckhbh %[ftmp6], %[ftmp10], %[ftmp0] \n\t" "punpckhbh %[ftmp6], %[ftmp10], %[ftmp0] \n\t"
@@ -209,6 +206,7 @@ void ff_pred8x8l_top_dc_8_mmi(uint8_t *src, int has_topleft,
[ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]), [ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]),
[ftmp10]"=&f"(ftmp[10]), [ftmp10]"=&f"(ftmp[10]),
[tmp0]"=&r"(tmp[0]), [tmp1]"=&r"(tmp[1]), [tmp0]"=&r"(tmp[0]), [tmp1]"=&r"(tmp[1]),
RESTRICT_ASM_ALL64
[dc]"=r"(dc) [dc]"=r"(dc)
: [srcA]"r"((mips_reg)(src-stride-1)), : [srcA]"r"((mips_reg)(src-stride-1)),
[src0]"r"((mips_reg)(src-stride)), [src0]"r"((mips_reg)(src-stride)),
@@ -221,20 +219,22 @@ void ff_pred8x8l_top_dc_8_mmi(uint8_t *src, int has_topleft,
__asm__ volatile ( __asm__ volatile (
"dli %[tmp0], 0x02 \n\t" "dli %[tmp0], 0x02 \n\t"
"punpcklwd %[ftmp0], %[dc], %[dc] \n\t" "punpcklwd %[ftmp0], %[dc], %[dc] \n\t"

"1: \n\t" "1: \n\t"
"gssdlc1 %[ftmp0], 0x07(%[src]) \n\t"
"gssdrc1 %[ftmp0], 0x00(%[src]) \n\t"
"gssdxc1 %[ftmp0], 0x00(%[src], %[stride]) \n\t"
MMI_SDC1(%[ftmp0], %[src], 0x00)
MMI_SDXC1(%[ftmp0], %[src], %[stride], 0x00)
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"gssdlc1 %[ftmp0], 0x07(%[src]) \n\t"
"gssdrc1 %[ftmp0], 0x00(%[src]) \n\t"
"gssdxc1 %[ftmp0], 0x00(%[src], %[stride]) \n\t"
MMI_SDC1(%[ftmp0], %[src], 0x00)
MMI_SDXC1(%[ftmp0], %[src], %[stride], 0x00)
"daddi %[tmp0], %[tmp0], -0x01 \n\t" "daddi %[tmp0], %[tmp0], -0x01 \n\t"
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"bnez %[tmp0], 1b \n\t" "bnez %[tmp0], 1b \n\t"
: [ftmp0]"=&f"(ftmp[0]), [tmp0]"=&r"(tmp[0]), : [ftmp0]"=&f"(ftmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_ALL64
RESTRICT_ASM_ADDRT
[src]"+&r"(src) [src]"+&r"(src)
: [dc]"f"(dc), [stride]"r"((mips_reg)stride) : [dc]"f"(dc), [stride]"r"((mips_reg)stride)
: "memory" : "memory"
@@ -257,13 +257,13 @@ void ff_pred8x8l_dc_8_mmi(uint8_t *src, int has_topleft, int has_topright,
const int l6 = (src[-1+5*stride] + 2*src[-1+6*stride] + src[-1+7*stride] + 2) >> 2; const int l6 = (src[-1+5*stride] + 2*src[-1+6*stride] + src[-1+7*stride] + 2) >> 2;
const int l7 = (src[-1+6*stride] + 2*src[-1+7*stride] + src[-1+7*stride] + 2) >> 2; const int l7 = (src[-1+6*stride] + 2*src[-1+7*stride] + src[-1+7*stride] + 2) >> 2;


DECLARE_VAR_ALL64;
DECLARE_VAR_ADDRT;

__asm__ volatile ( __asm__ volatile (
"gsldlc1 %[ftmp4], 0x07(%[srcA]) \n\t"
"gsldrc1 %[ftmp4], 0x00(%[srcA]) \n\t"
"gsldlc1 %[ftmp5], 0x07(%[src0]) \n\t"
"gsldrc1 %[ftmp5], 0x00(%[src0]) \n\t"
"gsldlc1 %[ftmp6], 0x07(%[src1]) \n\t"
"gsldrc1 %[ftmp6], 0x00(%[src1]) \n\t"
MMI_ULDC1(%[ftmp4], %[srcA], 0x00)
MMI_ULDC1(%[ftmp5], %[src0], 0x00)
MMI_ULDC1(%[ftmp6], %[src1], 0x00)
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"dli %[tmp0], 0x03 \n\t" "dli %[tmp0], 0x03 \n\t"
"punpcklbh %[ftmp7], %[ftmp4], %[ftmp0] \n\t" "punpcklbh %[ftmp7], %[ftmp4], %[ftmp0] \n\t"
@@ -309,7 +309,9 @@ void ff_pred8x8l_dc_8_mmi(uint8_t *src, int has_topleft, int has_topright,
[ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]), [ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]),
[ftmp10]"=&f"(ftmp[10]), [ftmp11]"=&f"(ftmp[11]), [ftmp10]"=&f"(ftmp[10]), [ftmp11]"=&f"(ftmp[11]),
[ftmp12]"=&f"(ftmp[12]), [ftmp13]"=&f"(ftmp[13]), [ftmp12]"=&f"(ftmp[12]), [ftmp13]"=&f"(ftmp[13]),
[tmp0]"=&r"(tmp[0]), [dc2]"=r"(dc2)
[tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_ALL64
[dc2]"=r"(dc2)
: [srcA]"r"((mips_reg)(src-stride-1)), : [srcA]"r"((mips_reg)(src-stride-1)),
[src0]"r"((mips_reg)(src-stride)), [src0]"r"((mips_reg)(src-stride)),
[src1]"r"((mips_reg)(src-stride+1)), [src1]"r"((mips_reg)(src-stride+1)),
@@ -323,20 +325,22 @@ void ff_pred8x8l_dc_8_mmi(uint8_t *src, int has_topleft, int has_topright,
__asm__ volatile ( __asm__ volatile (
"dli %[tmp0], 0x02 \n\t" "dli %[tmp0], 0x02 \n\t"
"punpcklwd %[ftmp0], %[dc], %[dc] \n\t" "punpcklwd %[ftmp0], %[dc], %[dc] \n\t"

"1: \n\t" "1: \n\t"
"gssdlc1 %[ftmp0], 0x07(%[src]) \n\t"
"gssdrc1 %[ftmp0], 0x00(%[src]) \n\t"
"gssdxc1 %[ftmp0], 0x00(%[src], %[stride]) \n\t"
MMI_SDC1(%[ftmp0], %[src], 0x00)
MMI_SDXC1(%[ftmp0], %[src], %[stride], 0x00)
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"gssdlc1 %[ftmp0], 0x07(%[src]) \n\t"
"gssdrc1 %[ftmp0], 0x00(%[src]) \n\t"
"gssdxc1 %[ftmp0], 0x00(%[src], %[stride]) \n\t"
MMI_SDC1(%[ftmp0], %[src], 0x00)
MMI_SDXC1(%[ftmp0], %[src], %[stride], 0x00)
"daddi %[tmp0], %[tmp0], -0x01 \n\t" "daddi %[tmp0], %[tmp0], -0x01 \n\t"
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"bnez %[tmp0], 1b \n\t" "bnez %[tmp0], 1b \n\t"
: [ftmp0]"=&f"(ftmp[0]), [tmp0]"=&r"(tmp[0]), : [ftmp0]"=&f"(ftmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_ALL64
RESTRICT_ASM_ADDRT
[src]"+&r"(src) [src]"+&r"(src)
: [dc]"f"(dc), [stride]"r"((mips_reg)stride) : [dc]"f"(dc), [stride]"r"((mips_reg)stride)
: "memory" : "memory"
@@ -348,15 +352,13 @@ void ff_pred8x8l_vertical_8_mmi(uint8_t *src, int has_topleft,
{ {
double ftmp[12]; double ftmp[12];
mips_reg tmp[1]; mips_reg tmp[1];
DECLARE_VAR_ALL64;


__asm__ volatile ( __asm__ volatile (
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"gsldlc1 %[ftmp3], 0x07(%[srcA]) \n\t"
"gsldrc1 %[ftmp3], 0x00(%[srcA]) \n\t"
"gsldlc1 %[ftmp4], 0x07(%[src0]) \n\t"
"gsldrc1 %[ftmp4], 0x00(%[src0]) \n\t"
"gsldlc1 %[ftmp5], 0x07(%[src1]) \n\t"
"gsldrc1 %[ftmp5], 0x00(%[src1]) \n\t"
MMI_LDC1(%[ftmp3], %[srcA], 0x00)
MMI_LDC1(%[ftmp4], %[src0], 0x00)
MMI_LDC1(%[ftmp5], %[src1], 0x00)
"punpcklbh %[ftmp6], %[ftmp3], %[ftmp0] \n\t" "punpcklbh %[ftmp6], %[ftmp3], %[ftmp0] \n\t"
"punpckhbh %[ftmp7], %[ftmp3], %[ftmp0] \n\t" "punpckhbh %[ftmp7], %[ftmp3], %[ftmp0] \n\t"
"punpcklbh %[ftmp8], %[ftmp4], %[ftmp0] \n\t" "punpcklbh %[ftmp8], %[ftmp4], %[ftmp0] \n\t"
@@ -385,7 +387,7 @@ void ff_pred8x8l_vertical_8_mmi(uint8_t *src, int has_topleft,
"psrah %[ftmp6], %[ftmp6], %[ftmp1] \n\t" "psrah %[ftmp6], %[ftmp6], %[ftmp1] \n\t"
"psrah %[ftmp7], %[ftmp7], %[ftmp1] \n\t" "psrah %[ftmp7], %[ftmp7], %[ftmp1] \n\t"
"packushb %[ftmp4], %[ftmp6], %[ftmp7] \n\t" "packushb %[ftmp4], %[ftmp6], %[ftmp7] \n\t"
"sdc1 %[ftmp4], 0x00(%[src]) \n\t"
MMI_SDC1(%[ftmp4], %[src], 0x00)
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]), [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
@@ -393,6 +395,7 @@ void ff_pred8x8l_vertical_8_mmi(uint8_t *src, int has_topleft,
[ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]), [ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]),
[ftmp10]"=&f"(ftmp[10]), [ftmp11]"=&f"(ftmp[11]), [ftmp10]"=&f"(ftmp[10]), [ftmp11]"=&f"(ftmp[11]),
[tmp0]"=&r"(tmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_ALL64
[src]"=r"(src) [src]"=r"(src)
: [srcA]"r"((mips_reg)(src-stride-1)), : [srcA]"r"((mips_reg)(src-stride-1)),
[src0]"r"((mips_reg)(src-stride)), [src0]"r"((mips_reg)(src-stride)),
@@ -403,22 +406,21 @@ void ff_pred8x8l_vertical_8_mmi(uint8_t *src, int has_topleft,


__asm__ volatile ( __asm__ volatile (
"dli %[tmp0], 0x02 \n\t" "dli %[tmp0], 0x02 \n\t"

"1: \n\t" "1: \n\t"
"gssdlc1 %[ftmp0], 0x07(%[src]) \n\t"
"gssdrc1 %[ftmp0], 0x00(%[src]) \n\t"
MMI_SDC1(%[ftmp0], %[src], 0x00)
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"gssdlc1 %[ftmp0], 0x07(%[src]) \n\t"
"gssdrc1 %[ftmp0], 0x00(%[src]) \n\t"
MMI_SDC1(%[ftmp0], %[src], 0x00)
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"gssdlc1 %[ftmp0], 0x07(%[src]) \n\t"
"gssdrc1 %[ftmp0], 0x00(%[src]) \n\t"
MMI_SDC1(%[ftmp0], %[src], 0x00)
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"gssdlc1 %[ftmp0], 0x07(%[src]) \n\t"
"gssdrc1 %[ftmp0], 0x00(%[src]) \n\t"
MMI_SDC1(%[ftmp0], %[src], 0x00)
"daddi %[tmp0], %[tmp0], -0x01 \n\t" "daddi %[tmp0], %[tmp0], -0x01 \n\t"
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"bnez %[tmp0], 1b \n\t" "bnez %[tmp0], 1b \n\t"
: [ftmp0]"=&f"(ftmp[0]), [tmp0]"=&r"(tmp[0]), : [ftmp0]"=&f"(ftmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_ALL64
[src]"+&r"(src) [src]"+&r"(src)
: [stride]"r"((mips_reg)stride) : [stride]"r"((mips_reg)stride)
: "memory" : "memory"
@@ -433,19 +435,21 @@ void ff_pred4x4_dc_8_mmi(uint8_t *src, const uint8_t *topright,
+ src[-1+2*stride] + src[-1+3*stride] + 4) >>3; + src[-1+2*stride] + src[-1+3*stride] + 4) >>3;
uint64_t tmp[2]; uint64_t tmp[2];
mips_reg addr[1]; mips_reg addr[1];
DECLARE_VAR_ADDRT;


__asm__ volatile ( __asm__ volatile (
PTR_ADDU "%[tmp0], %[dc], $0 \n\t" PTR_ADDU "%[tmp0], %[dc], $0 \n\t"
"dmul %[tmp1], %[tmp0], %[ff_pb_1] \n\t" "dmul %[tmp1], %[tmp0], %[ff_pb_1] \n\t"
"xor %[addr0], %[addr0], %[addr0] \n\t" "xor %[addr0], %[addr0], %[addr0] \n\t"
"gsswx %[tmp1], 0x00(%[src], %[addr0]) \n\t"
MMI_SWX(%[tmp1], %[src], %[addr0], 0x00)
PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t" PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
"gsswx %[tmp1], 0x00(%[src], %[addr0]) \n\t"
MMI_SWX(%[tmp1], %[src], %[addr0], 0x00)
PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t" PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
"gsswx %[tmp1], 0x00(%[src], %[addr0]) \n\t"
MMI_SWX(%[tmp1], %[src], %[addr0], 0x00)
PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t" PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
"gsswx %[tmp1], 0x00(%[src], %[addr0]) \n\t"
MMI_SWX(%[tmp1], %[src], %[addr0], 0x00)
: [tmp0]"=&r"(tmp[0]), [tmp1]"=&r"(tmp[1]), : [tmp0]"=&r"(tmp[0]), [tmp1]"=&r"(tmp[1]),
RESTRICT_ASM_ADDRT
[addr0]"=&r"(addr[0]) [addr0]"=&r"(addr[0])
: [src]"r"((mips_reg)src), [stride]"r"((mips_reg)stride), : [src]"r"((mips_reg)src), [stride]"r"((mips_reg)stride),
[dc]"r"(dc), [ff_pb_1]"r"(ff_pb_1) [dc]"r"(dc), [ff_pb_1]"r"(ff_pb_1)
@@ -518,13 +522,13 @@ void ff_pred8x8_top_dc_8_mmi(uint8_t *src, ptrdiff_t stride)
double ftmp[4]; double ftmp[4];
uint64_t tmp[1]; uint64_t tmp[1];
mips_reg addr[1]; mips_reg addr[1];
DECLARE_VAR_ALL64;


__asm__ volatile ( __asm__ volatile (
"dli %[tmp0], 0x02 \n\t" "dli %[tmp0], 0x02 \n\t"
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
PTR_SUBU "%[addr0], %[src], %[stride] \n\t" PTR_SUBU "%[addr0], %[src], %[stride] \n\t"
"gsldlc1 %[ftmp1], 0x07(%[addr0]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[addr0]) \n\t"
MMI_LDC1(%[ftmp1], %[addr0], 0x00)
"punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t" "punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t"
"punpckhbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t" "punpckhbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
"biadd %[ftmp2], %[ftmp2] \n\t" "biadd %[ftmp2], %[ftmp2] \n\t"
@@ -539,32 +543,25 @@ void ff_pred8x8_top_dc_8_mmi(uint8_t *src, ptrdiff_t stride)
"psrlh %[ftmp2], %[ftmp2], %[ftmp1] \n\t" "psrlh %[ftmp2], %[ftmp2], %[ftmp1] \n\t"
"psrlh %[ftmp3], %[ftmp3], %[ftmp1] \n\t" "psrlh %[ftmp3], %[ftmp3], %[ftmp1] \n\t"
"packushb %[ftmp1], %[ftmp2], %[ftmp3] \n\t" "packushb %[ftmp1], %[ftmp2], %[ftmp3] \n\t"
"gssdlc1 %[ftmp1], 0x07(%[src]) \n\t"
"gssdrc1 %[ftmp1], 0x00(%[src]) \n\t"
MMI_SDC1(%[ftmp1], %[src], 0x00)
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"gssdlc1 %[ftmp1], 0x07(%[src]) \n\t"
"gssdrc1 %[ftmp1], 0x00(%[src]) \n\t"
MMI_SDC1(%[ftmp1], %[src], 0x00)
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"gssdlc1 %[ftmp1], 0x07(%[src]) \n\t"
"gssdrc1 %[ftmp1], 0x00(%[src]) \n\t"
MMI_SDC1(%[ftmp1], %[src], 0x00)
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"gssdlc1 %[ftmp1], 0x07(%[src]) \n\t"
"gssdrc1 %[ftmp1], 0x00(%[src]) \n\t"
MMI_SDC1(%[ftmp1], %[src], 0x00)
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"gssdlc1 %[ftmp1], 0x07(%[src]) \n\t"
"gssdrc1 %[ftmp1], 0x00(%[src]) \n\t"
MMI_SDC1(%[ftmp1], %[src], 0x00)
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"gssdlc1 %[ftmp1], 0x07(%[src]) \n\t"
"gssdrc1 %[ftmp1], 0x00(%[src]) \n\t"
MMI_SDC1(%[ftmp1], %[src], 0x00)
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"gssdlc1 %[ftmp1], 0x07(%[src]) \n\t"
"gssdrc1 %[ftmp1], 0x00(%[src]) \n\t"
MMI_SDC1(%[ftmp1], %[src], 0x00)
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"gssdlc1 %[ftmp1], 0x07(%[src]) \n\t"
"gssdrc1 %[ftmp1], 0x00(%[src]) \n\t"
MMI_SDC1(%[ftmp1], %[src], 0x00)
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
[tmp0]"=&r"(tmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_ALL64
[addr0]"=&r"(addr[0]), [addr0]"=&r"(addr[0]),
[src]"+&r"(src) [src]"+&r"(src)
: [stride]"r"((mips_reg)stride) : [stride]"r"((mips_reg)stride)
@@ -651,21 +648,21 @@ void ff_pred8x8_dc_8_mmi(uint8_t *src, ptrdiff_t stride)
"packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t" "packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
"packushb %[ftmp2], %[ftmp3], %[ftmp4] \n\t" "packushb %[ftmp2], %[ftmp3], %[ftmp4] \n\t"
PTR_ADDU "%[addr0], $0, %[src] \n\t" PTR_ADDU "%[addr0], $0, %[src] \n\t"
"sdc1 %[ftmp1], 0x00(%[addr0]) \n\t"
MMI_SDC1(%[ftmp1], %[addr0], 0x00)
PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t" PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
"sdc1 %[ftmp1], 0x00(%[addr0]) \n\t"
MMI_SDC1(%[ftmp1], %[addr0], 0x00)
PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t" PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
"sdc1 %[ftmp1], 0x00(%[addr0]) \n\t"
MMI_SDC1(%[ftmp1], %[addr0], 0x00)
PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t" PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
"sdc1 %[ftmp1], 0x00(%[addr0]) \n\t"
MMI_SDC1(%[ftmp1], %[addr0], 0x00)
PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t" PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
"sdc1 %[ftmp2], 0x00(%[addr0]) \n\t"
MMI_SDC1(%[ftmp2], %[addr0], 0x00)
PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t" PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
"sdc1 %[ftmp2], 0x00(%[addr0]) \n\t"
MMI_SDC1(%[ftmp2], %[addr0], 0x00)
PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t" PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
"sdc1 %[ftmp2], 0x00(%[addr0]) \n\t"
MMI_SDC1(%[ftmp2], %[addr0], 0x00)
PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t" PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
"sdc1 %[ftmp2], 0x00(%[addr0]) \n\t"
MMI_SDC1(%[ftmp2], %[addr0], 0x00)
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
[ftmp4]"=&f"(ftmp[4]), [ftmp4]"=&f"(ftmp[4]),
@@ -682,28 +679,27 @@ void ff_pred8x16_vertical_8_mmi(uint8_t *src, ptrdiff_t stride)
{ {
double ftmp[1]; double ftmp[1];
uint64_t tmp[1]; uint64_t tmp[1];
DECLARE_VAR_ALL64;


__asm__ volatile ( __asm__ volatile (
"gsldlc1 %[ftmp0], 0x07(%[srcA]) \n\t"
"gsldrc1 %[ftmp0], 0x00(%[srcA]) \n\t"
MMI_LDC1(%[ftmp0], %[srcA], 0x00)
"dli %[tmp0], 0x04 \n\t" "dli %[tmp0], 0x04 \n\t"

"1: \n\t" "1: \n\t"
"gssdlc1 %[ftmp0], 0x07(%[src]) \n\t"
"gssdrc1 %[ftmp0], 0x00(%[src]) \n\t"
MMI_SDC1(%[ftmp0], %[src], 0x00)
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"gssdlc1 %[ftmp0], 0x07(%[src]) \n\t"
"gssdrc1 %[ftmp0], 0x00(%[src]) \n\t"
MMI_SDC1(%[ftmp0], %[src], 0x00)
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"gssdlc1 %[ftmp0], 0x07(%[src]) \n\t"
"gssdrc1 %[ftmp0], 0x00(%[src]) \n\t"
MMI_SDC1(%[ftmp0], %[src], 0x00)
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"gssdlc1 %[ftmp0], 0x07(%[src]) \n\t"
"gssdrc1 %[ftmp0], 0x00(%[src]) \n\t"
MMI_SDC1(%[ftmp0], %[src], 0x00)
"daddi %[tmp0], %[tmp0], -0x01 \n\t" "daddi %[tmp0], %[tmp0], -0x01 \n\t"
PTR_ADDU "%[src], %[src], %[stride] \n\t" PTR_ADDU "%[src], %[src], %[stride] \n\t"
"bnez %[tmp0], 1b \n\t" "bnez %[tmp0], 1b \n\t"
: [ftmp0]"=&f"(ftmp[0]), : [ftmp0]"=&f"(ftmp[0]),
[tmp0]"=&r"(tmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_ALL64
[src]"+&r"(src) [src]"+&r"(src)
: [stride]"r"((mips_reg)stride), [srcA]"r"((mips_reg)(src-stride)) : [stride]"r"((mips_reg)stride), [srcA]"r"((mips_reg)(src-stride))
: "memory" : "memory"
@@ -747,17 +743,16 @@ static inline void pred16x16_plane_compat_mmi(uint8_t *src, int stride,
const int svq3, const int rv40) const int svq3, const int rv40)
{ {
double ftmp[11]; double ftmp[11];
uint64_t tmp[7];
uint64_t tmp[6];
mips_reg addr[1]; mips_reg addr[1];
DECLARE_VAR_ALL64;


__asm__ volatile( __asm__ volatile(
PTR_SUBU "%[addr0], %[src], %[stride] \n\t" PTR_SUBU "%[addr0], %[src], %[stride] \n\t"
"dli %[tmp2], 0x20 \n\t"
"dmtc1 %[tmp2], %[ftmp4] \n\t"
"gsldlc1 %[ftmp0], 0x06(%[addr0]) \n\t"
"gsldlc1 %[ftmp2], 0x0f(%[addr0]) \n\t"
"gsldrc1 %[ftmp0], -0x01(%[addr0]) \n\t"
"gsldrc1 %[ftmp2], 0x08(%[addr0]) \n\t"
"dli %[tmp0], 0x20 \n\t"
"dmtc1 %[tmp0], %[ftmp4] \n\t"
MMI_ULDC1(%[ftmp0], %[addr0], -0x01)
MMI_ULDC1(%[ftmp2], %[addr0], 0x08)
"dsrl %[ftmp1], %[ftmp0], %[ftmp4] \n\t" "dsrl %[ftmp1], %[ftmp0], %[ftmp4] \n\t"
"dsrl %[ftmp3], %[ftmp2], %[ftmp4] \n\t" "dsrl %[ftmp3], %[ftmp2], %[ftmp4] \n\t"
"xor %[ftmp4], %[ftmp4], %[ftmp4] \n\t" "xor %[ftmp4], %[ftmp4], %[ftmp4] \n\t"
@@ -772,29 +767,29 @@ static inline void pred16x16_plane_compat_mmi(uint8_t *src, int stride,
"paddsh %[ftmp0], %[ftmp0], %[ftmp2] \n\t" "paddsh %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
"paddsh %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "paddsh %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
"paddsh %[ftmp0], %[ftmp0], %[ftmp1] \n\t" "paddsh %[ftmp0], %[ftmp0], %[ftmp1] \n\t"
"dli %[tmp2], 0x0e \n\t"
"dmtc1 %[tmp2], %[ftmp4] \n\t"
"dli %[tmp0], 0x0e \n\t"
"dmtc1 %[tmp0], %[ftmp4] \n\t"
"pshufh %[ftmp1], %[ftmp0], %[ftmp4] \n\t" "pshufh %[ftmp1], %[ftmp0], %[ftmp4] \n\t"
"paddsh %[ftmp0], %[ftmp0], %[ftmp1] \n\t" "paddsh %[ftmp0], %[ftmp0], %[ftmp1] \n\t"
"dli %[tmp2], 0x01 \n\t"
"dmtc1 %[tmp2], %[ftmp4] \n\t"
"dli %[tmp0], 0x01 \n\t"
"dmtc1 %[tmp0], %[ftmp4] \n\t"
"pshufh %[ftmp1], %[ftmp0], %[ftmp4] \n\t" "pshufh %[ftmp1], %[ftmp0], %[ftmp4] \n\t"
"paddsh %[ftmp5], %[ftmp0], %[ftmp1] \n\t" "paddsh %[ftmp5], %[ftmp0], %[ftmp1] \n\t"


PTR_ADDIU "%[addr0], %[src], -0x01 \n\t" PTR_ADDIU "%[addr0], %[src], -0x01 \n\t"
PTR_SUBU "%[addr0], %[addr0], %[stride] \n\t" PTR_SUBU "%[addr0], %[addr0], %[stride] \n\t"
"lbu %[tmp2], 0x00(%[addr0]) \n\t" "lbu %[tmp2], 0x00(%[addr0]) \n\t"
"lbu %[tmp6], 0x10(%[addr0]) \n\t"
"lbu %[tmp5], 0x10(%[addr0]) \n\t"
PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t" PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
"lbu %[tmp3], 0x00(%[addr0]) \n\t" "lbu %[tmp3], 0x00(%[addr0]) \n\t"
PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t" PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
"lbu %[tmp4], 0x00(%[addr0]) \n\t" "lbu %[tmp4], 0x00(%[addr0]) \n\t"
PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t" PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
"lbu %[tmp5], 0x00(%[addr0]) \n\t"
"lbu %[tmp0], 0x00(%[addr0]) \n\t"
"dsll %[tmp3], %[tmp3], 0x10 \n\t" "dsll %[tmp3], %[tmp3], 0x10 \n\t"
"dsll %[tmp4], %[tmp4], 0x20 \n\t" "dsll %[tmp4], %[tmp4], 0x20 \n\t"
"dsll %[tmp5], %[tmp5], 0x30 \n\t"
"or %[tmp4], %[tmp4], %[tmp5] \n\t"
"dsll %[tmp0], %[tmp0], 0x30 \n\t"
"or %[tmp4], %[tmp4], %[tmp0] \n\t"
"or %[tmp2], %[tmp2], %[tmp3] \n\t" "or %[tmp2], %[tmp2], %[tmp3] \n\t"
"or %[tmp2], %[tmp2], %[tmp4] \n\t" "or %[tmp2], %[tmp2], %[tmp4] \n\t"
"dmtc1 %[tmp2], %[ftmp0] \n\t" "dmtc1 %[tmp2], %[ftmp0] \n\t"
@@ -806,11 +801,11 @@ static inline void pred16x16_plane_compat_mmi(uint8_t *src, int stride,
PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t" PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
"lbu %[tmp4], 0x00(%[addr0]) \n\t" "lbu %[tmp4], 0x00(%[addr0]) \n\t"
PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t" PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
"lbu %[tmp5], 0x00(%[addr0]) \n\t"
"lbu %[tmp0], 0x00(%[addr0]) \n\t"
"dsll %[tmp3], %[tmp3], 0x10 \n\t" "dsll %[tmp3], %[tmp3], 0x10 \n\t"
"dsll %[tmp4], %[tmp4], 0x20 \n\t" "dsll %[tmp4], %[tmp4], 0x20 \n\t"
"dsll %[tmp5], %[tmp5], 0x30 \n\t"
"or %[tmp4], %[tmp4], %[tmp5] \n\t"
"dsll %[tmp0], %[tmp0], 0x30 \n\t"
"or %[tmp4], %[tmp4], %[tmp0] \n\t"
"or %[tmp2], %[tmp2], %[tmp3] \n\t" "or %[tmp2], %[tmp2], %[tmp3] \n\t"
"or %[tmp2], %[tmp2], %[tmp4] \n\t" "or %[tmp2], %[tmp2], %[tmp4] \n\t"
"dmtc1 %[tmp2], %[ftmp1] \n\t" "dmtc1 %[tmp2], %[ftmp1] \n\t"
@@ -823,11 +818,11 @@ static inline void pred16x16_plane_compat_mmi(uint8_t *src, int stride,
PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t" PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
"lbu %[tmp4], 0x00(%[addr0]) \n\t" "lbu %[tmp4], 0x00(%[addr0]) \n\t"
PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t" PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
"lbu %[tmp5], 0x00(%[addr0]) \n\t"
"lbu %[tmp0], 0x00(%[addr0]) \n\t"
"dsll %[tmp3], %[tmp3], 0x10 \n\t" "dsll %[tmp3], %[tmp3], 0x10 \n\t"
"dsll %[tmp4], %[tmp4], 0x20 \n\t" "dsll %[tmp4], %[tmp4], 0x20 \n\t"
"dsll %[tmp5], %[tmp5], 0x30 \n\t"
"or %[tmp4], %[tmp4], %[tmp5] \n\t"
"dsll %[tmp0], %[tmp0], 0x30 \n\t"
"or %[tmp4], %[tmp4], %[tmp0] \n\t"
"or %[tmp2], %[tmp2], %[tmp3] \n\t" "or %[tmp2], %[tmp2], %[tmp3] \n\t"
"or %[tmp2], %[tmp2], %[tmp4] \n\t" "or %[tmp2], %[tmp2], %[tmp4] \n\t"
"dmtc1 %[tmp2], %[ftmp2] \n\t" "dmtc1 %[tmp2], %[ftmp2] \n\t"
@@ -839,15 +834,15 @@ static inline void pred16x16_plane_compat_mmi(uint8_t *src, int stride,
PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t" PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
"lbu %[tmp4], 0x00(%[addr0]) \n\t" "lbu %[tmp4], 0x00(%[addr0]) \n\t"
PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t" PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
"lbu %[tmp5], 0x00(%[addr0]) \n\t"
"daddu %[tmp6], %[tmp6], %[tmp5] \n\t"
"daddiu %[tmp6], %[tmp6], 0x01 \n\t"
"dsll %[tmp6], %[tmp6], 0x04 \n\t"
"lbu %[tmp0], 0x00(%[addr0]) \n\t"
"daddu %[tmp5], %[tmp5], %[tmp0] \n\t"
"daddiu %[tmp5], %[tmp5], 0x01 \n\t"
"dsll %[tmp5], %[tmp5], 0x04 \n\t"


"dsll %[tmp3], %[tmp3], 0x10 \n\t" "dsll %[tmp3], %[tmp3], 0x10 \n\t"
"dsll %[tmp4], %[tmp4], 0x20 \n\t" "dsll %[tmp4], %[tmp4], 0x20 \n\t"
"dsll %[tmp5], %[tmp5], 0x30 \n\t"
"or %[tmp4], %[tmp4], %[tmp5] \n\t"
"dsll %[tmp0], %[tmp0], 0x30 \n\t"
"or %[tmp4], %[tmp4], %[tmp0] \n\t"
"or %[tmp2], %[tmp2], %[tmp3] \n\t" "or %[tmp2], %[tmp2], %[tmp3] \n\t"
"or %[tmp2], %[tmp2], %[tmp4] \n\t" "or %[tmp2], %[tmp2], %[tmp4] \n\t"
"dmtc1 %[tmp2], %[ftmp3] \n\t" "dmtc1 %[tmp2], %[ftmp3] \n\t"
@@ -859,13 +854,13 @@ static inline void pred16x16_plane_compat_mmi(uint8_t *src, int stride,
"paddsh %[ftmp0], %[ftmp0], %[ftmp2] \n\t" "paddsh %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
"paddsh %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "paddsh %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
"paddsh %[ftmp0], %[ftmp0], %[ftmp1] \n\t" "paddsh %[ftmp0], %[ftmp0], %[ftmp1] \n\t"
"dli %[tmp2], 0x0e \n\t"
"dmtc1 %[tmp2], %[ftmp4] \n\t"
"dli %[tmp0], 0x0e \n\t"
"dmtc1 %[tmp0], %[ftmp4] \n\t"
"pshufh %[ftmp1], %[ftmp0], %[ftmp4] \n\t" "pshufh %[ftmp1], %[ftmp0], %[ftmp4] \n\t"
"paddsh %[ftmp0], %[ftmp0], %[ftmp1] \n\t" "paddsh %[ftmp0], %[ftmp0], %[ftmp1] \n\t"


"dli %[tmp2], 0x01 \n\t"
"dmtc1 %[tmp2], %[ftmp4] \n\t"
"dli %[tmp0], 0x01 \n\t"
"dmtc1 %[tmp0], %[ftmp4] \n\t"
"pshufh %[ftmp1], %[ftmp0], %[ftmp4] \n\t" "pshufh %[ftmp1], %[ftmp0], %[ftmp4] \n\t"
"paddsh %[ftmp6], %[ftmp0], %[ftmp1] \n\t" "paddsh %[ftmp6], %[ftmp0], %[ftmp1] \n\t"


@@ -914,17 +909,17 @@ static inline void pred16x16_plane_compat_mmi(uint8_t *src, int stride,
"daddu %[tmp3], %[tmp0], %[tmp1] \n\t" "daddu %[tmp3], %[tmp0], %[tmp1] \n\t"
"dli %[tmp2], 0x07 \n\t" "dli %[tmp2], 0x07 \n\t"
"dmul %[tmp3], %[tmp3], %[tmp2] \n\t" "dmul %[tmp3], %[tmp3], %[tmp2] \n\t"
"dsubu %[tmp6], %[tmp6], %[tmp3] \n\t"
"dsubu %[tmp5], %[tmp5], %[tmp3] \n\t"


"xor %[ftmp4], %[ftmp4], %[ftmp4] \n\t" "xor %[ftmp4], %[ftmp4], %[ftmp4] \n\t"
"dmtc1 %[tmp0], %[ftmp0] \n\t" "dmtc1 %[tmp0], %[ftmp0] \n\t"
"pshufh %[ftmp0], %[ftmp0], %[ftmp4] \n\t" "pshufh %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
"dmtc1 %[tmp1], %[ftmp5] \n\t" "dmtc1 %[tmp1], %[ftmp5] \n\t"
"pshufh %[ftmp5], %[ftmp5], %[ftmp4] \n\t" "pshufh %[ftmp5], %[ftmp5], %[ftmp4] \n\t"
"dmtc1 %[tmp6], %[ftmp6] \n\t"
"dmtc1 %[tmp5], %[ftmp6] \n\t"
"pshufh %[ftmp6], %[ftmp6], %[ftmp4] \n\t" "pshufh %[ftmp6], %[ftmp6], %[ftmp4] \n\t"
"dli %[tmp2], 0x05 \n\t"
"dmtc1 %[tmp2], %[ftmp7] \n\t"
"dli %[tmp0], 0x05 \n\t"
"dmtc1 %[tmp0], %[ftmp7] \n\t"
"pmullh %[ftmp1], %[ff_pw_0to3], %[ftmp0] \n\t" "pmullh %[ftmp1], %[ff_pw_0to3], %[ftmp0] \n\t"
"dmtc1 %[ff_pw_4to7], %[ftmp2] \n\t" "dmtc1 %[ff_pw_4to7], %[ftmp2] \n\t"
"pmullh %[ftmp2], %[ftmp2], %[ftmp0] \n\t" "pmullh %[ftmp2], %[ftmp2], %[ftmp0] \n\t"
@@ -941,16 +936,14 @@ static inline void pred16x16_plane_compat_mmi(uint8_t *src, int stride,
"paddsh %[ftmp9], %[ftmp2], %[ftmp6] \n\t" "paddsh %[ftmp9], %[ftmp2], %[ftmp6] \n\t"
"psrah %[ftmp9], %[ftmp9], %[ftmp7] \n\t" "psrah %[ftmp9], %[ftmp9], %[ftmp7] \n\t"
"packushb %[ftmp0], %[ftmp8], %[ftmp9] \n\t" "packushb %[ftmp0], %[ftmp8], %[ftmp9] \n\t"
"gssdlc1 %[ftmp0], 0x07(%[addr0]) \n\t"
"gssdrc1 %[ftmp0], 0x00(%[addr0]) \n\t"
MMI_SDC1(%[ftmp0], %[addr0], 0x00)


"paddsh %[ftmp8], %[ftmp3], %[ftmp6] \n\t" "paddsh %[ftmp8], %[ftmp3], %[ftmp6] \n\t"
"psrah %[ftmp8], %[ftmp8], %[ftmp7] \n\t" "psrah %[ftmp8], %[ftmp8], %[ftmp7] \n\t"
"paddsh %[ftmp9], %[ftmp4], %[ftmp6] \n\t" "paddsh %[ftmp9], %[ftmp4], %[ftmp6] \n\t"
"psrah %[ftmp9], %[ftmp9], %[ftmp7] \n\t" "psrah %[ftmp9], %[ftmp9], %[ftmp7] \n\t"
"packushb %[ftmp0], %[ftmp8], %[ftmp9] \n\t" "packushb %[ftmp0], %[ftmp8], %[ftmp9] \n\t"
"gssdlc1 %[ftmp0], 0x0f(%[addr0]) \n\t"
"gssdrc1 %[ftmp0], 0x08(%[addr0]) \n\t"
MMI_SDC1(%[ftmp0], %[addr0], 0x08)


"paddsh %[ftmp6], %[ftmp6], %[ftmp5] \n\t" "paddsh %[ftmp6], %[ftmp6], %[ftmp5] \n\t"
PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t" PTR_ADDU "%[addr0], %[addr0], %[stride] \n\t"
@@ -964,7 +957,7 @@ static inline void pred16x16_plane_compat_mmi(uint8_t *src, int stride,
[tmp0]"=&r"(tmp[0]), [tmp1]"=&r"(tmp[1]), [tmp0]"=&r"(tmp[0]), [tmp1]"=&r"(tmp[1]),
[tmp2]"=&r"(tmp[2]), [tmp3]"=&r"(tmp[3]), [tmp2]"=&r"(tmp[2]), [tmp3]"=&r"(tmp[3]),
[tmp4]"=&r"(tmp[4]), [tmp5]"=&r"(tmp[5]), [tmp4]"=&r"(tmp[4]), [tmp5]"=&r"(tmp[5]),
[tmp6]"=&r"(tmp[6]),
RESTRICT_ASM_ALL64
[addr0]"=&r"(addr[0]) [addr0]"=&r"(addr[0])
: [src]"r"(src), [stride]"r"((mips_reg)stride), : [src]"r"(src), [stride]"r"((mips_reg)stride),
[svq3]"r"(svq3), [rv40]"r"(rv40), [svq3]"r"(svq3), [rv40]"r"(rv40),


+ 324
- 453
libavcodec/mips/h264qpel_mmi.c
File diff suppressed because it is too large
View File


+ 241
- 308
libavcodec/mips/hpeldsp_mmi.c View File

@@ -23,7 +23,7 @@


#include "hpeldsp_mips.h" #include "hpeldsp_mips.h"
#include "libavcodec/bit_depth_template.c" #include "libavcodec/bit_depth_template.c"
#include "libavutil/mips/asmdefs.h"
#include "libavutil/mips/mmiutils.h"
#include "constants.h" #include "constants.h"


void ff_put_pixels4_8_mmi(uint8_t *block, const uint8_t *pixels, void ff_put_pixels4_8_mmi(uint8_t *block, const uint8_t *pixels,
@@ -31,36 +31,34 @@ void ff_put_pixels4_8_mmi(uint8_t *block, const uint8_t *pixels,
{ {
double ftmp[2]; double ftmp[2];
mips_reg addr[2]; mips_reg addr[2];
uint64_t low32;
DECLARE_VAR_LOW32;
DECLARE_VAR_ADDRT;


__asm__ volatile ( __asm__ volatile (
PTR_ADDU "%[addr1], %[line_size], %[line_size] \n\t" PTR_ADDU "%[addr1], %[line_size], %[line_size] \n\t"
"1: \n\t" "1: \n\t"
PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t" PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t"
"uld %[low32], 0x00(%[pixels]) \n\t"
"mtc1 %[low32], %[ftmp0] \n\t"
"uld %[low32], 0x00(%[addr0]) \n\t"
"mtc1 %[low32], %[ftmp1] \n\t"
"swc1 %[ftmp0], 0x00(%[block]) \n\t"
"gsswxc1 %[ftmp1], 0x00(%[block], %[line_size]) \n\t"
MMI_ULWC1(%[ftmp0], %[pixels], 0x00)
MMI_ULWC1(%[ftmp1], %[addr0], 0x00)
MMI_SWC1(%[ftmp0], %[block], 0x00)
MMI_SWXC1(%[ftmp1], %[block], %[line_size], 0x00)
PTR_ADDU "%[pixels], %[pixels], %[addr1] \n\t" PTR_ADDU "%[pixels], %[pixels], %[addr1] \n\t"
PTR_ADDU "%[block], %[block], %[addr1] \n\t" PTR_ADDU "%[block], %[block], %[addr1] \n\t"


PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t" PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t"
"uld %[low32], 0x00(%[pixels]) \n\t"
"mtc1 %[low32], %[ftmp0] \n\t"
"uld %[low32], 0x00(%[addr0]) \n\t"
"mtc1 %[low32], %[ftmp1] \n\t"
"swc1 %[ftmp0], 0x00(%[block]) \n\t"
"gsswxc1 %[ftmp1], 0x00(%[block], %[line_size]) \n\t"
MMI_ULWC1(%[ftmp0], %[pixels], 0x00)
MMI_ULWC1(%[ftmp1], %[addr0], 0x00)
MMI_SWC1(%[ftmp0], %[block], 0x00)
MMI_SWXC1(%[ftmp1], %[block], %[line_size], 0x00)
PTR_ADDU "%[pixels], %[pixels], %[addr1] \n\t" PTR_ADDU "%[pixels], %[pixels], %[addr1] \n\t"
PTR_ADDU "%[block], %[block], %[addr1] \n\t" PTR_ADDU "%[block], %[block], %[addr1] \n\t"


PTR_ADDI "%[h], %[h], -0x04 \n\t" PTR_ADDI "%[h], %[h], -0x04 \n\t"
"bnez %[h], 1b \n\t" "bnez %[h], 1b \n\t"
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
RESTRICT_ASM_LOW32
RESTRICT_ASM_ADDRT
[addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]), [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
[low32]"=&r"(low32),
[block]"+&r"(block), [pixels]"+&r"(pixels), [block]"+&r"(block), [pixels]"+&r"(pixels),
[h]"+&r"(h) [h]"+&r"(h)
: [line_size]"r"((mips_reg)line_size) : [line_size]"r"((mips_reg)line_size)
@@ -72,35 +70,36 @@ void ff_put_pixels8_8_mmi(uint8_t *block, const uint8_t *pixels,
ptrdiff_t line_size, int h) ptrdiff_t line_size, int h)
{ {
double ftmp[2]; double ftmp[2];
mips_reg addr[2];
mips_reg addr[3];
DECLARE_VAR_ALL64;


__asm__ volatile ( __asm__ volatile (
PTR_ADDU "%[addr1], %[line_size], %[line_size] \n\t" PTR_ADDU "%[addr1], %[line_size], %[line_size] \n\t"
"1: \n\t" "1: \n\t"
"gsldlc1 %[ftmp0], 0x07(%[pixels]) \n\t"
MMI_ULDC1(%[ftmp0], %[pixels], 0x00)
PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t" PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t"
"gsldrc1 %[ftmp0], 0x00(%[pixels]) \n\t"
"gsldlc1 %[ftmp1], 0x07(%[addr0]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[addr0]) \n\t"
"sdc1 %[ftmp0], 0x00(%[block]) \n\t"
"gssdxc1 %[ftmp1], 0x00(%[block], %[line_size]) \n\t"
MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
MMI_SDC1(%[ftmp0], %[block], 0x00)
PTR_ADDU "%[addr2], %[block], %[line_size] \n\t"
MMI_SDC1(%[ftmp1], %[addr2], 0x00)
PTR_ADDU "%[pixels], %[pixels], %[addr1] \n\t" PTR_ADDU "%[pixels], %[pixels], %[addr1] \n\t"
PTR_ADDU "%[block], %[block], %[addr1] \n\t" PTR_ADDU "%[block], %[block], %[addr1] \n\t"


"gsldlc1 %[ftmp0], 0x07(%[pixels]) \n\t"
MMI_ULDC1(%[ftmp0], %[pixels], 0x00)
PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t" PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t"
"gsldrc1 %[ftmp0], 0x00(%[pixels]) \n\t"
"gsldlc1 %[ftmp1], 0x07(%[addr0]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[addr0]) \n\t"
"sdc1 %[ftmp0], 0x00(%[block]) \n\t"
"gssdxc1 %[ftmp1], 0x00(%[block], %[line_size]) \n\t"
MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
MMI_SDC1(%[ftmp0], %[block], 0x00)
PTR_ADDU "%[addr2], %[block], %[line_size] \n\t"
MMI_SDC1(%[ftmp1], %[addr2], 0x00)
PTR_ADDU "%[pixels], %[pixels], %[addr1] \n\t" PTR_ADDU "%[pixels], %[pixels], %[addr1] \n\t"
PTR_ADDU "%[block], %[block], %[addr1] \n\t" PTR_ADDU "%[block], %[block], %[addr1] \n\t"


PTR_ADDI "%[h], %[h], -0x04 \n\t" PTR_ADDI "%[h], %[h], -0x04 \n\t"
"bnez %[h], 1b \n\t" "bnez %[h], 1b \n\t"
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
RESTRICT_ASM_ALL64
[addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]), [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
[addr2]"=&r"(addr[2]),
[block]"+&r"(block), [pixels]"+&r"(pixels), [block]"+&r"(block), [pixels]"+&r"(pixels),
[h]"+&r"(h) [h]"+&r"(h)
: [line_size]"r"((mips_reg)line_size) : [line_size]"r"((mips_reg)line_size)
@@ -113,39 +112,33 @@ void ff_put_pixels16_8_mmi(uint8_t *block, const uint8_t *pixels,
{ {
double ftmp[4]; double ftmp[4];
mips_reg addr[2]; mips_reg addr[2];
DECLARE_VAR_ALL64;
DECLARE_VAR_ADDRT;


__asm__ volatile ( __asm__ volatile (
PTR_ADDU "%[addr1], %[line_size], %[line_size] \n\t" PTR_ADDU "%[addr1], %[line_size], %[line_size] \n\t"
"1: \n\t" "1: \n\t"
"gsldlc1 %[ftmp0], 0x07(%[pixels]) \n\t"
PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t" PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t"
"gsldrc1 %[ftmp0], 0x00(%[pixels]) \n\t"
"gsldlc1 %[ftmp2], 0x0f(%[pixels]) \n\t"
"gsldrc1 %[ftmp2], 0x08(%[pixels]) \n\t"
"gsldlc1 %[ftmp1], 0x07(%[addr0]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[addr0]) \n\t"
"gsldlc1 %[ftmp3], 0x0f(%[addr0]) \n\t"
"gsldrc1 %[ftmp3], 0x08(%[addr0]) \n\t"
"sdc1 %[ftmp0], 0x00(%[block]) \n\t"
"gssdxc1 %[ftmp1], 0x00(%[block], %[line_size]) \n\t"
"sdc1 %[ftmp2], 0x08(%[block]) \n\t"
"gssdxc1 %[ftmp3], 0x08(%[block], %[line_size]) \n\t"
MMI_ULDC1(%[ftmp0], %[pixels], 0x00)
MMI_ULDC1(%[ftmp2], %[pixels], 0x08)
MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
MMI_ULDC1(%[ftmp3], %[addr0], 0x08)
MMI_SDC1(%[ftmp0], %[block], 0x00)
MMI_SDXC1(%[ftmp1], %[block], %[line_size], 0x00)
MMI_SDC1(%[ftmp2], %[block], 0x08)
MMI_SDXC1(%[ftmp3], %[block], %[line_size], 0x08)
PTR_ADDU "%[pixels], %[pixels], %[addr1] \n\t" PTR_ADDU "%[pixels], %[pixels], %[addr1] \n\t"
PTR_ADDU "%[block], %[block], %[addr1] \n\t" PTR_ADDU "%[block], %[block], %[addr1] \n\t"


"gsldlc1 %[ftmp0], 0x07(%[pixels]) \n\t"
PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t" PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t"
"gsldrc1 %[ftmp0], 0x00(%[pixels]) \n\t"
"gsldlc1 %[ftmp2], 0x0f(%[pixels]) \n\t"
"gsldrc1 %[ftmp2], 0x08(%[pixels]) \n\t"
"gsldlc1 %[ftmp1], 0x07(%[addr0]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[addr0]) \n\t"
"gsldlc1 %[ftmp3], 0x0f(%[addr0]) \n\t"
"gsldrc1 %[ftmp3], 0x08(%[addr0]) \n\t"
"sdc1 %[ftmp0], 0x00(%[block]) \n\t"
"gssdxc1 %[ftmp1], 0x00(%[block], %[line_size]) \n\t"
"sdc1 %[ftmp2], 0x08(%[block]) \n\t"
"gssdxc1 %[ftmp3], 0x08(%[block], %[line_size]) \n\t"
MMI_ULDC1(%[ftmp0], %[pixels], 0x00)
MMI_ULDC1(%[ftmp2], %[pixels], 0x08)
MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
MMI_ULDC1(%[ftmp3], %[addr0], 0x08)
MMI_SDC1(%[ftmp0], %[block], 0x00)
MMI_SDXC1(%[ftmp1], %[block], %[line_size], 0x00)
MMI_SDC1(%[ftmp2], %[block], 0x08)
MMI_SDXC1(%[ftmp3], %[block], %[line_size], 0x08)
PTR_ADDU "%[pixels], %[pixels], %[addr1] \n\t" PTR_ADDU "%[pixels], %[pixels], %[addr1] \n\t"
PTR_ADDU "%[block], %[block], %[addr1] \n\t" PTR_ADDU "%[block], %[block], %[addr1] \n\t"


@@ -153,6 +146,8 @@ void ff_put_pixels16_8_mmi(uint8_t *block, const uint8_t *pixels,
"bnez %[h], 1b \n\t" "bnez %[h], 1b \n\t"
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
RESTRICT_ASM_ALL64
RESTRICT_ASM_ADDRT
[addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]), [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
[block]"+&r"(block), [pixels]"+&r"(pixels), [block]"+&r"(block), [pixels]"+&r"(pixels),
[h]"+&r"(h) [h]"+&r"(h)
@@ -166,42 +161,35 @@ void ff_avg_pixels4_8_mmi(uint8_t *block, const uint8_t *pixels,
{ {
double ftmp[4]; double ftmp[4];
mips_reg addr[3]; mips_reg addr[3];
uint64_t low32;
DECLARE_VAR_LOW32;
DECLARE_VAR_ADDRT;


__asm__ volatile ( __asm__ volatile (
PTR_ADDU "%[addr2], %[line_size], %[line_size] \n\t" PTR_ADDU "%[addr2], %[line_size], %[line_size] \n\t"
"1: \n\t" "1: \n\t"
PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t" PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t"
"uld %[low32], 0x00(%[pixels]) \n\t"
"mtc1 %[low32], %[ftmp0] \n\t"
"uld %[low32], 0x00(%[addr0]) \n\t"
"mtc1 %[low32], %[ftmp1] \n\t"
MMI_ULWC1(%[ftmp0], %[pixels], 0x00)
MMI_ULWC1(%[ftmp1], %[addr0], 0x00)
PTR_ADDU "%[addr1], %[block], %[line_size] \n\t" PTR_ADDU "%[addr1], %[block], %[line_size] \n\t"
"uld %[low32], 0x00(%[block]) \n\t"
"mtc1 %[low32], %[ftmp2] \n\t"
"uld %[low32], 0x00(%[addr1]) \n\t"
"mtc1 %[low32], %[ftmp3] \n\t"
MMI_ULWC1(%[ftmp2], %[block], 0x00)
MMI_ULWC1(%[ftmp3], %[addr1], 0x00)
"pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t" "pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
"pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
"swc1 %[ftmp0], 0x00(%[block]) \n\t"
"gsswxc1 %[ftmp1], 0x00(%[block], %[line_size]) \n\t"
MMI_SWC1(%[ftmp0], %[block], 0x00)
MMI_SWXC1(%[ftmp1], %[block], %[line_size], 0x00)
PTR_ADDU "%[pixels], %[pixels], %[addr2] \n\t" PTR_ADDU "%[pixels], %[pixels], %[addr2] \n\t"
PTR_ADDU "%[block], %[block], %[addr2] \n\t" PTR_ADDU "%[block], %[block], %[addr2] \n\t"


PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t" PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t"
"uld %[low32], 0x00(%[pixels]) \n\t"
"mtc1 %[low32], %[ftmp0] \n\t"
"uld %[low32], 0x00(%[addr0]) \n\t"
"mtc1 %[low32], %[ftmp1] \n\t"
MMI_ULWC1(%[ftmp0], %[pixels], 0x00)
MMI_ULWC1(%[ftmp1], %[addr0], 0x00)
PTR_ADDU "%[addr1], %[block], %[line_size] \n\t" PTR_ADDU "%[addr1], %[block], %[line_size] \n\t"
"uld %[low32], 0x00(%[block]) \n\t"
"mtc1 %[low32], %[ftmp2] \n\t"
"uld %[low32], 0x00(%[addr1]) \n\t"
"mtc1 %[low32], %[ftmp3] \n\t"
MMI_ULWC1(%[ftmp2], %[block], 0x00)
MMI_ULWC1(%[ftmp3], %[addr1], 0x00)
"pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t" "pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
"pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
"swc1 %[ftmp0], 0x00(%[block]) \n\t"
"gsswxc1 %[ftmp1], 0x00(%[block], %[line_size]) \n\t"
MMI_SWC1(%[ftmp0], %[block], 0x00)
MMI_SWXC1(%[ftmp1], %[block], %[line_size], 0x00)
PTR_ADDU "%[pixels], %[pixels], %[addr2] \n\t" PTR_ADDU "%[pixels], %[pixels], %[addr2] \n\t"
PTR_ADDU "%[block], %[block], %[addr2] \n\t" PTR_ADDU "%[block], %[block], %[addr2] \n\t"


@@ -209,9 +197,10 @@ void ff_avg_pixels4_8_mmi(uint8_t *block, const uint8_t *pixels,
"bnez %[h], 1b \n\t" "bnez %[h], 1b \n\t"
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
RESTRICT_ASM_LOW32
RESTRICT_ASM_ADDRT
[addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]), [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
[addr2]"=&r"(addr[2]), [addr2]"=&r"(addr[2]),
[low32]"=&r"(low32),
[block]"+&r"(block), [pixels]"+&r"(pixels), [block]"+&r"(block), [pixels]"+&r"(pixels),
[h]"+&r"(h) [h]"+&r"(h)
: [line_size]"r"((mips_reg)line_size) : [line_size]"r"((mips_reg)line_size)
@@ -224,41 +213,35 @@ void ff_avg_pixels8_8_mmi(uint8_t *block, const uint8_t *pixels,
{ {
double ftmp[4]; double ftmp[4];
mips_reg addr[3]; mips_reg addr[3];
DECLARE_VAR_ALL64;
DECLARE_VAR_ADDRT;


__asm__ volatile ( __asm__ volatile (
PTR_ADDU "%[addr2], %[line_size], %[line_size] \n\t" PTR_ADDU "%[addr2], %[line_size], %[line_size] \n\t"
"1: \n\t" "1: \n\t"
"gsldlc1 %[ftmp0], 0x07(%[pixels]) \n\t"
MMI_ULDC1(%[ftmp0], %[pixels], 0x00)
PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t" PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t"
"gsldrc1 %[ftmp0], 0x00(%[pixels]) \n\t"
"gsldlc1 %[ftmp1], 0x07(%[addr0]) \n\t"
MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
PTR_ADDU "%[addr1], %[block], %[line_size] \n\t" PTR_ADDU "%[addr1], %[block], %[line_size] \n\t"
"gsldrc1 %[ftmp1], 0x00(%[addr0]) \n\t"
"gsldlc1 %[ftmp2], 0x07(%[block]) \n\t"
"gsldrc1 %[ftmp2], 0x00(%[block]) \n\t"
"gsldlc1 %[ftmp3], 0x07(%[addr1]) \n\t"
"gsldrc1 %[ftmp3], 0x00(%[addr1]) \n\t"
MMI_ULDC1(%[ftmp2], %[block], 0x00)
MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
"pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t" "pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
"pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
"sdc1 %[ftmp0], 0x00(%[block]) \n\t"
"gssdxc1 %[ftmp1], 0x00(%[block], %[line_size]) \n\t"
MMI_SDC1(%[ftmp0], %[block], 0x00)
MMI_SDXC1(%[ftmp1], %[block], %[line_size], 0x00)
PTR_ADDU "%[pixels], %[pixels], %[addr2] \n\t" PTR_ADDU "%[pixels], %[pixels], %[addr2] \n\t"
PTR_ADDU "%[block], %[block], %[addr2] \n\t" PTR_ADDU "%[block], %[block], %[addr2] \n\t"


"gsldlc1 %[ftmp0], 0x07(%[pixels]) \n\t"
MMI_ULDC1(%[ftmp0], %[pixels], 0x00)
PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t" PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t"
"gsldrc1 %[ftmp0], 0x00(%[pixels]) \n\t"
"gsldlc1 %[ftmp1], 0x07(%[addr0]) \n\t"
MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
PTR_ADDU "%[addr1], %[block], %[line_size] \n\t" PTR_ADDU "%[addr1], %[block], %[line_size] \n\t"
"gsldrc1 %[ftmp1], 0x00(%[addr0]) \n\t"
"gsldlc1 %[ftmp2], 0x07(%[block]) \n\t"
"gsldrc1 %[ftmp2], 0x00(%[block]) \n\t"
"gsldlc1 %[ftmp3], 0x07(%[addr1]) \n\t"
"gsldrc1 %[ftmp3], 0x00(%[addr1]) \n\t"
MMI_ULDC1(%[ftmp2], %[block], 0x00)
MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
"pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t" "pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
"pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
"sdc1 %[ftmp0], 0x00(%[block]) \n\t"
"gssdxc1 %[ftmp1], 0x00(%[block], %[line_size]) \n\t"
MMI_SDC1(%[ftmp0], %[block], 0x00)
MMI_SDXC1(%[ftmp1], %[block], %[line_size], 0x00)
PTR_ADDU "%[pixels], %[pixels], %[addr2] \n\t" PTR_ADDU "%[pixels], %[pixels], %[addr2] \n\t"
PTR_ADDU "%[block], %[block], %[addr2] \n\t" PTR_ADDU "%[block], %[block], %[addr2] \n\t"


@@ -266,6 +249,8 @@ void ff_avg_pixels8_8_mmi(uint8_t *block, const uint8_t *pixels,
"bnez %[h], 1b \n\t" "bnez %[h], 1b \n\t"
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
RESTRICT_ASM_ALL64
RESTRICT_ASM_ADDRT
[addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]), [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
[addr2]"=&r"(addr[2]), [addr2]"=&r"(addr[2]),
[block]"+&r"(block), [pixels]"+&r"(pixels), [block]"+&r"(block), [pixels]"+&r"(pixels),
@@ -280,65 +265,51 @@ void ff_avg_pixels16_8_mmi(uint8_t *block, const uint8_t *pixels,
{ {
double ftmp[8]; double ftmp[8];
mips_reg addr[3]; mips_reg addr[3];
DECLARE_VAR_ALL64;
DECLARE_VAR_ADDRT;


__asm__ volatile ( __asm__ volatile (
PTR_ADDU "%[addr2], %[line_size], %[line_size] \n\t" PTR_ADDU "%[addr2], %[line_size], %[line_size] \n\t"
"1: \n\t" "1: \n\t"
"gsldlc1 %[ftmp0], 0x07(%[pixels]) \n\t"
MMI_ULDC1(%[ftmp0], %[pixels], 0x00)
PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t" PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t"
"gsldrc1 %[ftmp0], 0x00(%[pixels]) \n\t"
"gsldlc1 %[ftmp4], 0x0f(%[pixels]) \n\t"
MMI_ULDC1(%[ftmp4], %[pixels], 0x08)
PTR_ADDU "%[addr1], %[block], %[line_size] \n\t" PTR_ADDU "%[addr1], %[block], %[line_size] \n\t"
"gsldrc1 %[ftmp4], 0x08(%[pixels]) \n\t"
"gsldlc1 %[ftmp1], 0x07(%[addr0]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[addr0]) \n\t"
"gsldlc1 %[ftmp5], 0x0f(%[addr0]) \n\t"
"gsldrc1 %[ftmp5], 0x08(%[addr0]) \n\t"
"gsldlc1 %[ftmp2], 0x07(%[block]) \n\t"
"gsldrc1 %[ftmp2], 0x00(%[block]) \n\t"
"gsldlc1 %[ftmp6], 0x0f(%[block]) \n\t"
"gsldrc1 %[ftmp6], 0x08(%[block]) \n\t"
"gsldlc1 %[ftmp3], 0x07(%[addr1]) \n\t"
"gsldrc1 %[ftmp3], 0x00(%[addr1]) \n\t"
"gsldlc1 %[ftmp7], 0x0f(%[addr1]) \n\t"
"gsldrc1 %[ftmp7], 0x08(%[addr1]) \n\t"
MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
MMI_ULDC1(%[ftmp5], %[addr0], 0x08)
MMI_ULDC1(%[ftmp2], %[block], 0x00)
MMI_ULDC1(%[ftmp6], %[block], 0x08)
MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
MMI_ULDC1(%[ftmp7], %[addr1], 0x08)
"pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t" "pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
"pavgb %[ftmp4], %[ftmp4], %[ftmp6] \n\t" "pavgb %[ftmp4], %[ftmp4], %[ftmp6] \n\t"
"pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
"pavgb %[ftmp5], %[ftmp5], %[ftmp7] \n\t" "pavgb %[ftmp5], %[ftmp5], %[ftmp7] \n\t"
"sdc1 %[ftmp0], 0x00(%[block]) \n\t"
"gssdxc1 %[ftmp1], 0x00(%[block], %[line_size]) \n\t"
"sdc1 %[ftmp4], 0x08(%[block]) \n\t"
"gssdxc1 %[ftmp5], 0x08(%[block], %[line_size]) \n\t"
MMI_SDC1(%[ftmp0], %[block], 0x00)
MMI_SDXC1(%[ftmp1], %[block], %[line_size], 0x00)
MMI_SDC1(%[ftmp4], %[block], 0x08)
MMI_SDXC1(%[ftmp5], %[block], %[line_size], 0x08)
PTR_ADDU "%[pixels], %[pixels], %[addr2] \n\t" PTR_ADDU "%[pixels], %[pixels], %[addr2] \n\t"
PTR_ADDU "%[block], %[block], %[addr2] \n\t" PTR_ADDU "%[block], %[block], %[addr2] \n\t"


"gsldlc1 %[ftmp0], 0x07(%[pixels]) \n\t"
MMI_ULDC1(%[ftmp0], %[pixels], 0x00)
PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t" PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t"
"gsldrc1 %[ftmp0], 0x00(%[pixels]) \n\t"
"gsldlc1 %[ftmp4], 0x0f(%[pixels]) \n\t"
MMI_ULDC1(%[ftmp4], %[pixels], 0x08)
PTR_ADDU "%[addr1], %[block], %[line_size] \n\t" PTR_ADDU "%[addr1], %[block], %[line_size] \n\t"
"gsldrc1 %[ftmp4], 0x08(%[pixels]) \n\t"
"gsldlc1 %[ftmp1], 0x07(%[addr0]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[addr0]) \n\t"
"gsldlc1 %[ftmp5], 0x0f(%[addr0]) \n\t"
"gsldrc1 %[ftmp5], 0x08(%[addr0]) \n\t"
"gsldlc1 %[ftmp2], 0x07(%[block]) \n\t"
"gsldrc1 %[ftmp2], 0x00(%[block]) \n\t"
"gsldlc1 %[ftmp6], 0x0f(%[block]) \n\t"
"gsldrc1 %[ftmp6], 0x08(%[block]) \n\t"
"gsldlc1 %[ftmp3], 0x07(%[addr1]) \n\t"
"gsldrc1 %[ftmp3], 0x00(%[addr1]) \n\t"
"gsldlc1 %[ftmp7], 0x0f(%[addr1]) \n\t"
"gsldrc1 %[ftmp7], 0x08(%[addr1]) \n\t"
MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
MMI_ULDC1(%[ftmp5], %[addr0], 0x08)
MMI_ULDC1(%[ftmp2], %[block], 0x00)
MMI_ULDC1(%[ftmp6], %[block], 0x08)
MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
MMI_ULDC1(%[ftmp7], %[addr1], 0x08)
"pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t" "pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
"pavgb %[ftmp4], %[ftmp4], %[ftmp6] \n\t" "pavgb %[ftmp4], %[ftmp4], %[ftmp6] \n\t"
"pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
"pavgb %[ftmp5], %[ftmp5], %[ftmp7] \n\t" "pavgb %[ftmp5], %[ftmp5], %[ftmp7] \n\t"
"sdc1 %[ftmp0], 0x00(%[block]) \n\t"
"gssdxc1 %[ftmp1], 0x00(%[block], %[line_size]) \n\t"
"sdc1 %[ftmp4], 0x08(%[block]) \n\t"
"gssdxc1 %[ftmp5], 0x08(%[block], %[line_size]) \n\t"
MMI_SDC1(%[ftmp0], %[block], 0x00)
MMI_SDXC1(%[ftmp1], %[block], %[line_size], 0x00)
MMI_SDC1(%[ftmp4], %[block], 0x08)
MMI_SDXC1(%[ftmp5], %[block], %[line_size], 0x08)
PTR_ADDU "%[pixels], %[pixels], %[addr2] \n\t" PTR_ADDU "%[pixels], %[pixels], %[addr2] \n\t"
PTR_ADDU "%[block], %[block], %[addr2] \n\t" PTR_ADDU "%[block], %[block], %[addr2] \n\t"


@@ -348,6 +319,8 @@ void ff_avg_pixels16_8_mmi(uint8_t *block, const uint8_t *pixels,
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]), [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]), [ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
RESTRICT_ASM_ALL64
RESTRICT_ASM_ADDRT
[addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]), [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
[addr2]"=&r"(addr[2]), [addr2]"=&r"(addr[2]),
[block]"+&r"(block), [pixels]"+&r"(pixels), [block]"+&r"(block), [pixels]"+&r"(pixels),
@@ -363,7 +336,8 @@ inline void ff_put_pixels4_l2_8_mmi(uint8_t *dst, const uint8_t *src1,
{ {
double ftmp[4]; double ftmp[4];
mips_reg addr[5]; mips_reg addr[5];
uint64_t low32;
DECLARE_VAR_LOW32;
DECLARE_VAR_ADDRT;


__asm__ volatile ( __asm__ volatile (
PTR_ADDU "%[addr2], %[src_stride1], %[src_stride1] \n\t" PTR_ADDU "%[addr2], %[src_stride1], %[src_stride1] \n\t"
@@ -371,38 +345,30 @@ inline void ff_put_pixels4_l2_8_mmi(uint8_t *dst, const uint8_t *src1,
PTR_ADDU "%[addr4], %[dst_stride], %[dst_stride] \n\t" PTR_ADDU "%[addr4], %[dst_stride], %[dst_stride] \n\t"
"1: \n\t" "1: \n\t"
PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t" PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t"
"uld %[low32], 0x00(%[src1]) \n\t"
"mtc1 %[low32], %[ftmp0] \n\t"
"uld %[low32], 0x00(%[addr0]) \n\t"
"mtc1 %[low32], %[ftmp1] \n\t"
"uld %[low32], 0x00(%[src2]) \n\t"
"mtc1 %[low32], %[ftmp2] \n\t"
MMI_ULWC1(%[ftmp0], %[src1], 0x00)
MMI_ULWC1(%[ftmp1], %[addr0], 0x00)
MMI_ULWC1(%[ftmp2], %[src2], 0x00)
PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t" PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
"uld %[low32], 0x00(%[addr1]) \n\t"
"mtc1 %[low32], %[ftmp3] \n\t"
MMI_ULWC1(%[ftmp3], %[addr1], 0x00)
PTR_ADDU "%[src1], %[src1], %[addr2] \n\t" PTR_ADDU "%[src1], %[src1], %[addr2] \n\t"
"pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t" "pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
"pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
"swc1 %[ftmp0], 0x00(%[dst]) \n\t"
"gsswxc1 %[ftmp1], 0x00(%[dst], %[dst_stride]) \n\t"
MMI_SWC1(%[ftmp0], %[dst], 0x00)
MMI_SWXC1(%[ftmp1], %[dst], %[dst_stride], 0x00)
PTR_ADDU "%[src2], %[src2], %[addr3] \n\t" PTR_ADDU "%[src2], %[src2], %[addr3] \n\t"
PTR_ADDU "%[dst], %[dst], %[addr4] \n\t" PTR_ADDU "%[dst], %[dst], %[addr4] \n\t"


PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t" PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t"
"uld %[low32], 0x00(%[src1]) \n\t"
"mtc1 %[low32], %[ftmp0] \n\t"
"uld %[low32], 0x00(%[addr0]) \n\t"
"mtc1 %[low32], %[ftmp1] \n\t"
"uld %[low32], 0x00(%[src2]) \n\t"
"mtc1 %[low32], %[ftmp2] \n\t"
MMI_ULWC1(%[ftmp0], %[src1], 0x00)
MMI_ULWC1(%[ftmp1], %[addr0], 0x00)
MMI_ULWC1(%[ftmp2], %[src2], 0x00)
PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t" PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
"uld %[low32], 0x00(%[addr1]) \n\t"
"mtc1 %[low32], %[ftmp3] \n\t"
MMI_ULWC1(%[ftmp3], %[addr1], 0x00)
PTR_ADDU "%[src1], %[src1], %[addr2] \n\t" PTR_ADDU "%[src1], %[src1], %[addr2] \n\t"
"pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t" "pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
"pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
"swc1 %[ftmp0], 0x00(%[dst]) \n\t"
"gsswxc1 %[ftmp1], 0x00(%[dst], %[dst_stride]) \n\t"
MMI_SWC1(%[ftmp0], %[dst], 0x00)
MMI_SWXC1(%[ftmp1], %[dst], %[dst_stride], 0x00)
PTR_ADDU "%[src2], %[src2], %[addr3] \n\t" PTR_ADDU "%[src2], %[src2], %[addr3] \n\t"
PTR_ADDU "%[dst], %[dst], %[addr4] \n\t" PTR_ADDU "%[dst], %[dst], %[addr4] \n\t"


@@ -410,10 +376,11 @@ inline void ff_put_pixels4_l2_8_mmi(uint8_t *dst, const uint8_t *src1,
"bnez %[h], 1b \n\t" "bnez %[h], 1b \n\t"
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
RESTRICT_ASM_LOW32
RESTRICT_ASM_ADDRT
[addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]), [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
[addr2]"=&r"(addr[2]), [addr3]"=&r"(addr[3]), [addr2]"=&r"(addr[2]), [addr3]"=&r"(addr[3]),
[addr4]"=&r"(addr[4]), [addr4]"=&r"(addr[4]),
[low32]"=&r"(low32),
[dst]"+&r"(dst), [src1]"+&r"(src1), [dst]"+&r"(dst), [src1]"+&r"(src1),
[src2]"+&r"(src2), [h]"+&r"(h) [src2]"+&r"(src2), [h]"+&r"(h)
: [dst_stride]"r"((mips_reg)dst_stride), : [dst_stride]"r"((mips_reg)dst_stride),
@@ -429,45 +396,40 @@ inline void ff_put_pixels8_l2_8_mmi(uint8_t *dst, const uint8_t *src1,
{ {
double ftmp[4]; double ftmp[4];
mips_reg addr[5]; mips_reg addr[5];
DECLARE_VAR_ALL64;
DECLARE_VAR_ADDRT;


__asm__ volatile ( __asm__ volatile (
PTR_ADDU "%[addr2], %[src_stride1], %[src_stride1] \n\t" PTR_ADDU "%[addr2], %[src_stride1], %[src_stride1] \n\t"
PTR_ADDU "%[addr3], %[src_stride2], %[src_stride2] \n\t" PTR_ADDU "%[addr3], %[src_stride2], %[src_stride2] \n\t"
PTR_ADDU "%[addr4], %[dst_stride], %[dst_stride] \n\t" PTR_ADDU "%[addr4], %[dst_stride], %[dst_stride] \n\t"

"1: \n\t" "1: \n\t"
"gsldlc1 %[ftmp0], 0x07(%[src1]) \n\t"
MMI_ULDC1(%[ftmp0], %[src1], 0x00)
PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t" PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t"
"gsldrc1 %[ftmp0], 0x00(%[src1]) \n\t"
"gsldlc1 %[ftmp1], 0x07(%[addr0]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[addr0]) \n\t"
"gsldlc1 %[ftmp2], 0x07(%[src2]) \n\t"
MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
MMI_ULDC1(%[ftmp2], %[src2], 0x00)
PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t" PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
"gsldrc1 %[ftmp2], 0x00(%[src2]) \n\t"
"gsldlc1 %[ftmp3], 0x07(%[addr1]) \n\t"
MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
PTR_ADDU "%[src1], %[src1], %[addr2] \n\t" PTR_ADDU "%[src1], %[src1], %[addr2] \n\t"
"gsldrc1 %[ftmp3], 0x00(%[addr1]) \n\t"
"pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t" "pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
"pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
"sdc1 %[ftmp0], 0x00(%[dst]) \n\t"
"gssdxc1 %[ftmp1], 0x00(%[dst], %[dst_stride]) \n\t"
MMI_SDC1(%[ftmp0], %[dst], 0x00)
MMI_SDXC1(%[ftmp1], %[dst], %[dst_stride], 0x00)
PTR_ADDU "%[src2], %[src2], %[addr3] \n\t" PTR_ADDU "%[src2], %[src2], %[addr3] \n\t"
PTR_ADDU "%[dst], %[dst], %[addr4] \n\t" PTR_ADDU "%[dst], %[dst], %[addr4] \n\t"


"gsldlc1 %[ftmp0], 0x07(%[src1]) \n\t"
MMI_ULDC1(%[ftmp0], %[src1], 0x00)
PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t" PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t"
"gsldrc1 %[ftmp0], 0x00(%[src1]) \n\t"
"gsldlc1 %[ftmp1], 0x07(%[addr0]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[addr0]) \n\t"
"gsldlc1 %[ftmp2], 0x07(%[src2]) \n\t"
MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
MMI_ULDC1(%[ftmp2], %[src2], 0x00)
PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t" PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
"gsldrc1 %[ftmp2], 0x00(%[src2]) \n\t"
"gsldlc1 %[ftmp3], 0x07(%[addr1]) \n\t"
MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
PTR_ADDU "%[src1], %[src1], %[addr2] \n\t" PTR_ADDU "%[src1], %[src1], %[addr2] \n\t"
"gsldrc1 %[ftmp3], 0x00(%[addr1]) \n\t"
"pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t" "pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
"pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
"sdc1 %[ftmp0], 0x00(%[dst]) \n\t"
"gssdxc1 %[ftmp1], 0x00(%[dst], %[dst_stride]) \n\t"
MMI_SDC1(%[ftmp0], %[dst], 0x00)
MMI_SDXC1(%[ftmp1], %[dst], %[dst_stride], 0x00)
PTR_ADDU "%[src2], %[src2], %[addr3] \n\t" PTR_ADDU "%[src2], %[src2], %[addr3] \n\t"
PTR_ADDU "%[dst], %[dst], %[addr4] \n\t" PTR_ADDU "%[dst], %[dst], %[addr4] \n\t"


@@ -475,6 +437,8 @@ inline void ff_put_pixels8_l2_8_mmi(uint8_t *dst, const uint8_t *src1,
"bnez %[h], 1b \n\t" "bnez %[h], 1b \n\t"
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
RESTRICT_ASM_ALL64
RESTRICT_ASM_ADDRT
[addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]), [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
[addr2]"=&r"(addr[2]), [addr3]"=&r"(addr[3]), [addr2]"=&r"(addr[2]), [addr3]"=&r"(addr[3]),
[addr4]"=&r"(addr[4]), [addr4]"=&r"(addr[4]),
@@ -493,69 +457,56 @@ inline void ff_put_pixels16_l2_8_mmi(uint8_t *dst, const uint8_t *src1,
{ {
double ftmp[8]; double ftmp[8];
mips_reg addr[5]; mips_reg addr[5];
DECLARE_VAR_ALL64;
DECLARE_VAR_ADDRT;


__asm__ volatile ( __asm__ volatile (
PTR_ADDU "%[addr2], %[src_stride1], %[src_stride1] \n\t" PTR_ADDU "%[addr2], %[src_stride1], %[src_stride1] \n\t"
PTR_ADDU "%[addr3], %[src_stride2], %[src_stride2] \n\t" PTR_ADDU "%[addr3], %[src_stride2], %[src_stride2] \n\t"
PTR_ADDU "%[addr4], %[dst_stride], %[dst_stride] \n\t" PTR_ADDU "%[addr4], %[dst_stride], %[dst_stride] \n\t"

"1: \n\t" "1: \n\t"
"gsldlc1 %[ftmp0], 0x07(%[src1]) \n\t"
MMI_ULDC1(%[ftmp0], %[src1], 0x00)
PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t" PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t"
"gsldrc1 %[ftmp0], 0x00(%[src1]) \n\t"
"gsldlc1 %[ftmp4], 0x0f(%[src1]) \n\t"
"gsldrc1 %[ftmp4], 0x08(%[src1]) \n\t"
"gsldlc1 %[ftmp1], 0x07(%[addr0]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[addr0]) \n\t"
"gsldlc1 %[ftmp5], 0x0f(%[addr0]) \n\t"
"gsldrc1 %[ftmp5], 0x08(%[addr0]) \n\t"
"gsldlc1 %[ftmp2], 0x07(%[src2]) \n\t"
MMI_ULDC1(%[ftmp4], %[src1], 0x08)
MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
MMI_ULDC1(%[ftmp5], %[addr0], 0x08)
MMI_ULDC1(%[ftmp2], %[src2], 0x00)
PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t" PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
"gsldrc1 %[ftmp2], 0x00(%[src2]) \n\t"
"gsldlc1 %[ftmp6], 0x0f(%[src2]) \n\t"
"gsldrc1 %[ftmp6], 0x08(%[src2]) \n\t"
"gsldlc1 %[ftmp3], 0x07(%[addr1]) \n\t"
MMI_ULDC1(%[ftmp6], %[src2], 0x08)
MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
PTR_ADDU "%[src1], %[src1], %[addr2] \n\t" PTR_ADDU "%[src1], %[src1], %[addr2] \n\t"
"gsldrc1 %[ftmp3], 0x00(%[addr1]) \n\t"
"gsldlc1 %[ftmp7], 0x0f(%[addr1]) \n\t"
"gsldrc1 %[ftmp7], 0x08(%[addr1]) \n\t"
MMI_ULDC1(%[ftmp7], %[addr1], 0x08)
"pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t" "pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
"pavgb %[ftmp4], %[ftmp4], %[ftmp6] \n\t" "pavgb %[ftmp4], %[ftmp4], %[ftmp6] \n\t"
"pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
"pavgb %[ftmp5], %[ftmp5], %[ftmp7] \n\t" "pavgb %[ftmp5], %[ftmp5], %[ftmp7] \n\t"
"sdc1 %[ftmp0], 0x00(%[dst]) \n\t"
"gssdxc1 %[ftmp1], 0x00(%[dst], %[dst_stride]) \n\t"
"sdc1 %[ftmp4], 0x08(%[dst]) \n\t"
"gssdxc1 %[ftmp5], 0x08(%[dst], %[dst_stride]) \n\t"
MMI_SDC1(%[ftmp0], %[dst], 0x00)
MMI_SDXC1(%[ftmp1], %[dst], %[dst_stride], 0x00)
MMI_SDC1(%[ftmp4], %[dst], 0x08)
MMI_SDXC1(%[ftmp5], %[dst], %[dst_stride], 0x08)
PTR_ADDU "%[src2], %[src2], %[addr3] \n\t" PTR_ADDU "%[src2], %[src2], %[addr3] \n\t"
PTR_ADDU "%[dst], %[dst], %[addr4] \n\t" PTR_ADDU "%[dst], %[dst], %[addr4] \n\t"


"gsldlc1 %[ftmp0], 0x07(%[src1]) \n\t"
MMI_ULDC1(%[ftmp0], %[src1], 0x00)
PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t" PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t"
"gsldrc1 %[ftmp0], 0x00(%[src1]) \n\t"
"gsldlc1 %[ftmp4], 0x0f(%[src1]) \n\t"
"gsldrc1 %[ftmp4], 0x08(%[src1]) \n\t"
"gsldlc1 %[ftmp1], 0x07(%[addr0]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[addr0]) \n\t"
"gsldlc1 %[ftmp5], 0x0f(%[addr0]) \n\t"
"gsldrc1 %[ftmp5], 0x08(%[addr0]) \n\t"
"gsldlc1 %[ftmp2], 0x07(%[src2]) \n\t"
MMI_ULDC1(%[ftmp4], %[src1], 0x08)
MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
MMI_ULDC1(%[ftmp5], %[addr0], 0x08)
MMI_ULDC1(%[ftmp2], %[src2], 0x00)
PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t" PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
"gsldrc1 %[ftmp2], 0x00(%[src2]) \n\t"
"gsldlc1 %[ftmp6], 0x0f(%[src2]) \n\t"
"gsldrc1 %[ftmp6], 0x08(%[src2]) \n\t"
"gsldlc1 %[ftmp3], 0x07(%[addr1]) \n\t"
MMI_ULDC1(%[ftmp6], %[src2], 0x08)
MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
PTR_ADDU "%[src1], %[src1], %[addr2] \n\t" PTR_ADDU "%[src1], %[src1], %[addr2] \n\t"
"gsldrc1 %[ftmp3], 0x00(%[addr1]) \n\t"
"gsldlc1 %[ftmp7], 0x0f(%[addr1]) \n\t"
"gsldrc1 %[ftmp7], 0x08(%[addr1]) \n\t"
MMI_ULDC1(%[ftmp7], %[addr1], 0x08)
"pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t" "pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
"pavgb %[ftmp4], %[ftmp4], %[ftmp6] \n\t" "pavgb %[ftmp4], %[ftmp4], %[ftmp6] \n\t"
"pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
"pavgb %[ftmp5], %[ftmp5], %[ftmp7] \n\t" "pavgb %[ftmp5], %[ftmp5], %[ftmp7] \n\t"
"sdc1 %[ftmp0], 0x00(%[dst]) \n\t"
"gssdxc1 %[ftmp1], 0x00(%[dst], %[dst_stride]) \n\t"
"sdc1 %[ftmp4], 0x08(%[dst]) \n\t"
"gssdxc1 %[ftmp5], 0x08(%[dst], %[dst_stride]) \n\t"
MMI_SDC1(%[ftmp0], %[dst], 0x00)
MMI_SDXC1(%[ftmp1], %[dst], %[dst_stride], 0x00)
MMI_SDC1(%[ftmp4], %[dst], 0x08)
MMI_SDXC1(%[ftmp5], %[dst], %[dst_stride], 0x08)
PTR_ADDU "%[src2], %[src2], %[addr3] \n\t" PTR_ADDU "%[src2], %[src2], %[addr3] \n\t"
PTR_ADDU "%[dst], %[dst], %[addr4] \n\t" PTR_ADDU "%[dst], %[dst], %[addr4] \n\t"


@@ -565,6 +516,8 @@ inline void ff_put_pixels16_l2_8_mmi(uint8_t *dst, const uint8_t *src1,
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]), [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]), [ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
RESTRICT_ASM_ALL64
RESTRICT_ASM_ADDRT
[addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]), [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
[addr2]"=&r"(addr[2]), [addr3]"=&r"(addr[3]), [addr2]"=&r"(addr[2]), [addr3]"=&r"(addr[3]),
[addr4]"=&r"(addr[4]), [addr4]"=&r"(addr[4]),
@@ -583,60 +536,50 @@ inline void ff_avg_pixels4_l2_8_mmi(uint8_t *dst, const uint8_t *src1,
{ {
double ftmp[6]; double ftmp[6];
mips_reg addr[6]; mips_reg addr[6];
uint64_t low32;
DECLARE_VAR_LOW32;
DECLARE_VAR_ADDRT;


__asm__ volatile ( __asm__ volatile (
PTR_ADDU "%[addr2], %[src_stride1], %[src_stride1] \n\t" PTR_ADDU "%[addr2], %[src_stride1], %[src_stride1] \n\t"
PTR_ADDU "%[addr3], %[src_stride2], %[src_stride2] \n\t" PTR_ADDU "%[addr3], %[src_stride2], %[src_stride2] \n\t"
PTR_ADDU "%[addr4], %[dst_stride], %[dst_stride] \n\t" PTR_ADDU "%[addr4], %[dst_stride], %[dst_stride] \n\t"

"1: \n\t" "1: \n\t"
PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t" PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t"
"uld %[low32], 0x00(%[src1]) \n\t"
"mtc1 %[low32], %[ftmp0] \n\t"
"uld %[low32], 0x00(%[addr0]) \n\t"
"mtc1 %[low32], %[ftmp1] \n\t"
"uld %[low32], 0x00(%[src2]) \n\t"
"mtc1 %[low32], %[ftmp2] \n\t"
MMI_ULWC1(%[ftmp0], %[src1], 0x00)
MMI_ULWC1(%[ftmp1], %[addr0], 0x00)
MMI_ULWC1(%[ftmp2], %[src2], 0x00)
PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t" PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
"uld %[low32], 0x00(%[addr1]) \n\t"
"mtc1 %[low32], %[ftmp3] \n\t"
MMI_ULWC1(%[ftmp3], %[addr1], 0x00)
PTR_ADDU "%[src1], %[src1], %[addr2] \n\t" PTR_ADDU "%[src1], %[src1], %[addr2] \n\t"
"pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t" "pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
"pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
PTR_ADDU "%[addr5], %[dst], %[dst_stride] \n\t" PTR_ADDU "%[addr5], %[dst], %[dst_stride] \n\t"
"uld %[low32], 0x00(%[dst]) \n\t"
"mtc1 %[low32], %[ftmp4] \n\t"
"uld %[low32], 0x00(%[addr5]) \n\t"
"mtc1 %[low32], %[ftmp5] \n\t"
MMI_ULWC1(%[ftmp4], %[dst], 0x00)
MMI_ULWC1(%[ftmp5], %[addr5], 0x00)
"pavgb %[ftmp0], %[ftmp0], %[ftmp4] \n\t" "pavgb %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
"pavgb %[ftmp1], %[ftmp1], %[ftmp5] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp5] \n\t"
"swc1 %[ftmp0], 0x00(%[dst]) \n\t"
"gsswxc1 %[ftmp1], 0x00(%[dst], %[dst_stride]) \n\t"
MMI_SWC1(%[ftmp0], %[dst], 0x00)
MMI_SWXC1(%[ftmp1], %[dst], %[dst_stride], 0x00)
PTR_ADDU "%[src2], %[src2], %[addr3] \n\t" PTR_ADDU "%[src2], %[src2], %[addr3] \n\t"
PTR_ADDU "%[dst], %[dst], %[addr4] \n\t" PTR_ADDU "%[dst], %[dst], %[addr4] \n\t"


PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t" PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t"
"uld %[low32], 0x00(%[src1]) \n\t"
"mtc1 %[low32], %[ftmp0] \n\t"
"uld %[low32], 0x00(%[addr0]) \n\t"
"mtc1 %[low32], %[ftmp1] \n\t"
"uld %[low32], 0x00(%[src2]) \n\t"
"mtc1 %[low32], %[ftmp2] \n\t"
MMI_ULWC1(%[ftmp0], %[src1], 0x00)
MMI_ULWC1(%[ftmp1], %[addr0], 0x00)
MMI_ULWC1(%[ftmp2], %[src2], 0x00)
PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t" PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
"uld %[low32], 0x00(%[addr1]) \n\t"
"mtc1 %[low32], %[ftmp3] \n\t"
MMI_ULWC1(%[ftmp3], %[addr1], 0x00)
PTR_ADDU "%[src1], %[src1], %[addr2] \n\t" PTR_ADDU "%[src1], %[src1], %[addr2] \n\t"
"pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t" "pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
"pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
PTR_ADDU "%[addr5], %[dst], %[dst_stride] \n\t" PTR_ADDU "%[addr5], %[dst], %[dst_stride] \n\t"
"uld %[low32], 0x00(%[dst]) \n\t"
"mtc1 %[low32], %[ftmp4] \n\t"
"uld %[low32], 0x00(%[addr5]) \n\t"
"mtc1 %[low32], %[ftmp5] \n\t"
MMI_ULWC1(%[ftmp4], %[dst], 0x00)
MMI_ULWC1(%[ftmp5], %[addr5], 0x00)
"pavgb %[ftmp0], %[ftmp0], %[ftmp4] \n\t" "pavgb %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
"pavgb %[ftmp1], %[ftmp1], %[ftmp5] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp5] \n\t"
"swc1 %[ftmp0], 0x00(%[dst]) \n\t"
"gsswxc1 %[ftmp1], 0x00(%[dst], %[dst_stride]) \n\t"
MMI_SWC1(%[ftmp0], %[dst], 0x00)
MMI_SWXC1(%[ftmp1], %[dst], %[dst_stride], 0x00)
PTR_ADDU "%[src2], %[src2], %[addr3] \n\t" PTR_ADDU "%[src2], %[src2], %[addr3] \n\t"
PTR_ADDU "%[dst], %[dst], %[addr4] \n\t" PTR_ADDU "%[dst], %[dst], %[addr4] \n\t"


@@ -645,10 +588,11 @@ inline void ff_avg_pixels4_l2_8_mmi(uint8_t *dst, const uint8_t *src1,
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]), [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
RESTRICT_ASM_LOW32
RESTRICT_ASM_ADDRT
[addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]), [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
[addr2]"=&r"(addr[2]), [addr3]"=&r"(addr[3]), [addr2]"=&r"(addr[2]), [addr3]"=&r"(addr[3]),
[addr4]"=&r"(addr[4]), [addr5]"=&r"(addr[5]), [addr4]"=&r"(addr[4]), [addr5]"=&r"(addr[5]),
[low32]"=&r"(low32),
[dst]"+&r"(dst), [src1]"+&r"(src1), [dst]"+&r"(dst), [src1]"+&r"(src1),
[src2]"+&r"(src2), [h]"+&r"(h) [src2]"+&r"(src2), [h]"+&r"(h)
: [dst_stride]"r"((mips_reg)dst_stride), : [dst_stride]"r"((mips_reg)dst_stride),
@@ -664,59 +608,50 @@ inline void ff_avg_pixels8_l2_8_mmi(uint8_t *dst, const uint8_t *src1,
{ {
double ftmp[6]; double ftmp[6];
mips_reg addr[6]; mips_reg addr[6];
DECLARE_VAR_ALL64;
DECLARE_VAR_ADDRT;


__asm__ volatile ( __asm__ volatile (
PTR_ADDU "%[addr2], %[src_stride1], %[src_stride1] \n\t" PTR_ADDU "%[addr2], %[src_stride1], %[src_stride1] \n\t"
PTR_ADDU "%[addr3], %[src_stride2], %[src_stride2] \n\t" PTR_ADDU "%[addr3], %[src_stride2], %[src_stride2] \n\t"
PTR_ADDU "%[addr4], %[dst_stride], %[dst_stride] \n\t" PTR_ADDU "%[addr4], %[dst_stride], %[dst_stride] \n\t"

"1: \n\t" "1: \n\t"
"gsldlc1 %[ftmp0], 0x07(%[src1]) \n\t"
MMI_ULDC1(%[ftmp0], %[src1], 0x00)
PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t" PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t"
"gsldrc1 %[ftmp0], 0x00(%[src1]) \n\t"
"gsldlc1 %[ftmp1], 0x07(%[addr0]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[addr0]) \n\t"
"gsldlc1 %[ftmp2], 0x07(%[src2]) \n\t"
MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t" PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
"gsldrc1 %[ftmp2], 0x00(%[src2]) \n\t"
"gsldlc1 %[ftmp3], 0x07(%[addr1]) \n\t"
MMI_ULDC1(%[ftmp2], %[src2], 0x00)
MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
PTR_ADDU "%[src1], %[src1], %[addr2] \n\t" PTR_ADDU "%[src1], %[src1], %[addr2] \n\t"
"gsldrc1 %[ftmp3], 0x00(%[addr1]) \n\t"
"pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t" "pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
"pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
PTR_ADDU "%[addr5], %[dst], %[dst_stride] \n\t" PTR_ADDU "%[addr5], %[dst], %[dst_stride] \n\t"
"gsldlc1 %[ftmp4], 0x07(%[dst]) \n\t"
"gsldrc1 %[ftmp4], 0x00(%[dst]) \n\t"
"gsldlc1 %[ftmp5], 0x07(%[addr5]) \n\t"
"gsldrc1 %[ftmp5], 0x00(%[addr5]) \n\t"
MMI_ULDC1(%[ftmp4], %[dst], 0x00)
MMI_ULDC1(%[ftmp5], %[addr5], 0x00)
"pavgb %[ftmp0], %[ftmp0], %[ftmp4] \n\t" "pavgb %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
"pavgb %[ftmp1], %[ftmp1], %[ftmp5] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp5] \n\t"
"sdc1 %[ftmp0], 0x00(%[dst]) \n\t"
"gssdxc1 %[ftmp1], 0x00(%[dst], %[dst_stride]) \n\t"
MMI_SDC1(%[ftmp0], %[dst], 0x00)
MMI_SDXC1(%[ftmp1], %[dst], %[dst_stride], 0x00)
PTR_ADDU "%[src2], %[src2], %[addr3] \n\t" PTR_ADDU "%[src2], %[src2], %[addr3] \n\t"
PTR_ADDU "%[dst], %[dst], %[addr4] \n\t" PTR_ADDU "%[dst], %[dst], %[addr4] \n\t"


"gsldlc1 %[ftmp0], 0x07(%[src1]) \n\t"
MMI_ULDC1(%[ftmp0], %[src1], 0x00)
PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t" PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t"
"gsldrc1 %[ftmp0], 0x00(%[src1]) \n\t"
"gsldlc1 %[ftmp1], 0x07(%[addr0]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[addr0]) \n\t"
"gsldlc1 %[ftmp2], 0x07(%[src2]) \n\t"
MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t" PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
"gsldrc1 %[ftmp2], 0x00(%[src2]) \n\t"
"gsldlc1 %[ftmp3], 0x07(%[addr1]) \n\t"
MMI_ULDC1(%[ftmp2], %[src2], 0x00)
MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
PTR_ADDU "%[src1], %[src1], %[addr2] \n\t" PTR_ADDU "%[src1], %[src1], %[addr2] \n\t"
"gsldrc1 %[ftmp3], 0x00(%[addr1]) \n\t"
"pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t" "pavgb %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
"pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
PTR_ADDU "%[addr5], %[dst], %[dst_stride] \n\t" PTR_ADDU "%[addr5], %[dst], %[dst_stride] \n\t"
"gsldlc1 %[ftmp4], 0x07(%[dst]) \n\t"
"gsldrc1 %[ftmp4], 0x00(%[dst]) \n\t"
"gsldlc1 %[ftmp5], 0x07(%[addr5]) \n\t"
"gsldrc1 %[ftmp5], 0x00(%[addr5]) \n\t"
MMI_ULDC1(%[ftmp4], %[dst], 0x00)
MMI_ULDC1(%[ftmp5], %[addr5], 0x00)
"pavgb %[ftmp0], %[ftmp0], %[ftmp4] \n\t" "pavgb %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
"pavgb %[ftmp1], %[ftmp1], %[ftmp5] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp5] \n\t"
"sdc1 %[ftmp0], 0x00(%[dst]) \n\t"
"gssdxc1 %[ftmp1], 0x00(%[dst], %[dst_stride]) \n\t"
MMI_SDC1(%[ftmp0], %[dst], 0x00)
MMI_SDXC1(%[ftmp1], %[dst], %[dst_stride], 0x00)
PTR_ADDU "%[src2], %[src2], %[addr3] \n\t" PTR_ADDU "%[src2], %[src2], %[addr3] \n\t"
PTR_ADDU "%[dst], %[dst], %[addr4] \n\t" PTR_ADDU "%[dst], %[dst], %[addr4] \n\t"


@@ -725,6 +660,8 @@ inline void ff_avg_pixels8_l2_8_mmi(uint8_t *dst, const uint8_t *src1,
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]), [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
RESTRICT_ASM_ALL64
RESTRICT_ASM_ADDRT
[addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]), [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
[addr2]"=&r"(addr[2]), [addr3]"=&r"(addr[3]), [addr2]"=&r"(addr[2]), [addr3]"=&r"(addr[3]),
[addr4]"=&r"(addr[4]), [addr5]"=&r"(addr[5]), [addr4]"=&r"(addr[4]), [addr5]"=&r"(addr[5]),
@@ -795,24 +732,23 @@ inline void ff_put_no_rnd_pixels8_l2_8_mmi(uint8_t *dst, const uint8_t *src1,
{ {
double ftmp[5]; double ftmp[5];
mips_reg addr[5]; mips_reg addr[5];
DECLARE_VAR_ALL64;
DECLARE_VAR_ADDRT;


__asm__ volatile ( __asm__ volatile (
"pcmpeqb %[ftmp4], %[ftmp4], %[ftmp4] \n\t" "pcmpeqb %[ftmp4], %[ftmp4], %[ftmp4] \n\t"
PTR_ADDU "%[addr2], %[src_stride1], %[src_stride1] \n\t" PTR_ADDU "%[addr2], %[src_stride1], %[src_stride1] \n\t"
PTR_ADDU "%[addr3], %[src_stride2], %[src_stride2] \n\t" PTR_ADDU "%[addr3], %[src_stride2], %[src_stride2] \n\t"
PTR_ADDU "%[addr4], %[dst_stride], %[dst_stride] \n\t" PTR_ADDU "%[addr4], %[dst_stride], %[dst_stride] \n\t"

"1: \n\t" "1: \n\t"
"gsldlc1 %[ftmp0], 0x07(%[src1]) \n\t"
MMI_ULDC1(%[ftmp0], %[src1], 0x00)
PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t" PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t"
"gsldrc1 %[ftmp0], 0x00(%[src1]) \n\t"
"gsldlc1 %[ftmp1], 0x07(%[addr0]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[addr0]) \n\t"
"gsldlc1 %[ftmp2], 0x07(%[src2]) \n\t"
MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
MMI_ULDC1(%[ftmp2], %[src2], 0x00)
PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t" PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
"gsldrc1 %[ftmp2], 0x00(%[src2]) \n\t"
"gsldlc1 %[ftmp3], 0x07(%[addr1]) \n\t"
MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
PTR_ADDU "%[src1], %[src1], %[addr2] \n\t" PTR_ADDU "%[src1], %[src1], %[addr2] \n\t"
"gsldrc1 %[ftmp3], 0x00(%[addr1]) \n\t"
"xor %[ftmp0], %[ftmp0], %[ftmp4] \n\t" "xor %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
"xor %[ftmp1], %[ftmp1], %[ftmp4] \n\t" "xor %[ftmp1], %[ftmp1], %[ftmp4] \n\t"
"xor %[ftmp2], %[ftmp2], %[ftmp4] \n\t" "xor %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
@@ -821,22 +757,18 @@ inline void ff_put_no_rnd_pixels8_l2_8_mmi(uint8_t *dst, const uint8_t *src1,
"pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
"xor %[ftmp0], %[ftmp0], %[ftmp4] \n\t" "xor %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
"xor %[ftmp1], %[ftmp1], %[ftmp4] \n\t" "xor %[ftmp1], %[ftmp1], %[ftmp4] \n\t"
"sdc1 %[ftmp0], 0x00(%[dst]) \n\t"
"gssdxc1 %[ftmp1], 0x00(%[dst], %[dst_stride]) \n\t"
MMI_SDC1(%[ftmp0], %[dst], 0x00)
MMI_SDXC1(%[ftmp1], %[dst], %[dst_stride], 0x00)
PTR_ADDU "%[src2], %[src2], %[addr3] \n\t" PTR_ADDU "%[src2], %[src2], %[addr3] \n\t"
PTR_ADDU "%[dst], %[dst], %[addr4] \n\t" PTR_ADDU "%[dst], %[dst], %[addr4] \n\t"


"gsldlc1 %[ftmp0], 0x07(%[src1]) \n\t"
MMI_ULDC1(%[ftmp0], %[src1], 0x00)
PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t" PTR_ADDU "%[addr0], %[src1], %[src_stride1] \n\t"
"gsldrc1 %[ftmp0], 0x00(%[src1]) \n\t"
"gsldlc1 %[ftmp1], 0x07(%[addr0]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[addr0]) \n\t"
"gsldlc1 %[ftmp2], 0x07(%[src2]) \n\t"
MMI_ULDC1(%[ftmp1], %[addr0], 0x00)
MMI_ULDC1(%[ftmp2], %[src2], 0x00)
PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t" PTR_ADDU "%[addr1], %[src2], %[src_stride2] \n\t"
"gsldrc1 %[ftmp2], 0x00(%[src2]) \n\t"
"gsldlc1 %[ftmp3], 0x07(%[addr1]) \n\t"
MMI_ULDC1(%[ftmp3], %[addr1], 0x00)
PTR_ADDU "%[src1], %[src1], %[addr2] \n\t" PTR_ADDU "%[src1], %[src1], %[addr2] \n\t"
"gsldrc1 %[ftmp3], 0x00(%[addr1]) \n\t"
"xor %[ftmp0], %[ftmp0], %[ftmp4] \n\t" "xor %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
"xor %[ftmp1], %[ftmp1], %[ftmp4] \n\t" "xor %[ftmp1], %[ftmp1], %[ftmp4] \n\t"
"xor %[ftmp2], %[ftmp2], %[ftmp4] \n\t" "xor %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
@@ -845,8 +777,8 @@ inline void ff_put_no_rnd_pixels8_l2_8_mmi(uint8_t *dst, const uint8_t *src1,
"pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "pavgb %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
"xor %[ftmp0], %[ftmp0], %[ftmp4] \n\t" "xor %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
"xor %[ftmp1], %[ftmp1], %[ftmp4] \n\t" "xor %[ftmp1], %[ftmp1], %[ftmp4] \n\t"
"sdc1 %[ftmp0], 0x00(%[dst]) \n\t"
"gssdxc1 %[ftmp1], 0x00(%[dst], %[dst_stride]) \n\t"
MMI_SDC1(%[ftmp0], %[dst], 0x00)
MMI_SDXC1(%[ftmp1], %[dst], %[dst_stride], 0x00)
PTR_ADDU "%[src2], %[src2], %[addr3] \n\t" PTR_ADDU "%[src2], %[src2], %[addr3] \n\t"
PTR_ADDU "%[dst], %[dst], %[addr4] \n\t" PTR_ADDU "%[dst], %[dst], %[addr4] \n\t"


@@ -855,6 +787,8 @@ inline void ff_put_no_rnd_pixels8_l2_8_mmi(uint8_t *dst, const uint8_t *src1,
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
[ftmp4]"=&f"(ftmp[4]), [ftmp4]"=&f"(ftmp[4]),
RESTRICT_ASM_ALL64
RESTRICT_ASM_ADDRT
[addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]), [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
[addr2]"=&r"(addr[2]), [addr3]"=&r"(addr[3]), [addr2]"=&r"(addr[2]), [addr3]"=&r"(addr[3]),
[addr4]"=&r"(addr[4]), [addr4]"=&r"(addr[4]),
@@ -981,6 +915,8 @@ void ff_put_pixels8_xy2_8_mmi(uint8_t *block, const uint8_t *pixels,
#if 1 #if 1
double ftmp[10]; double ftmp[10];
mips_reg addr[2]; mips_reg addr[2];
DECLARE_VAR_ALL64;
DECLARE_VAR_ADDRT;


__asm__ volatile ( __asm__ volatile (
"xor %[ftmp7], %[ftmp7], %[ftmp7] \n\t" "xor %[ftmp7], %[ftmp7], %[ftmp7] \n\t"
@@ -993,11 +929,9 @@ void ff_put_pixels8_xy2_8_mmi(uint8_t *block, const uint8_t *pixels,
"psllh %[ftmp6], %[ftmp6], %[ftmp8] \n\t" "psllh %[ftmp6], %[ftmp6], %[ftmp8] \n\t"


"dli %[addr0], 0x02 \n\t" "dli %[addr0], 0x02 \n\t"
"gsldlc1 %[ftmp0], 0x07(%[pixels]) \n\t"
"gsldrc1 %[ftmp0], 0x00(%[pixels]) \n\t"
"dmtc1 %[addr0], %[ftmp9] \n\t" "dmtc1 %[addr0], %[ftmp9] \n\t"
"gsldlc1 %[ftmp4], 0x08(%[pixels]) \n\t"
"gsldrc1 %[ftmp4], 0x01(%[pixels]) \n\t"
MMI_ULDC1(%[ftmp0], %[pixels], 0x00)
MMI_ULDC1(%[ftmp4], %[pixels], 0x01)
"mov.d %[ftmp1], %[ftmp0] \n\t" "mov.d %[ftmp1], %[ftmp0] \n\t"
"mov.d %[ftmp5], %[ftmp4] \n\t" "mov.d %[ftmp5], %[ftmp4] \n\t"
"punpcklbh %[ftmp0], %[ftmp0], %[ftmp7] \n\t" "punpcklbh %[ftmp0], %[ftmp0], %[ftmp7] \n\t"
@@ -1009,12 +943,11 @@ void ff_put_pixels8_xy2_8_mmi(uint8_t *block, const uint8_t *pixels,
"xor %[addr0], %[addr0], %[addr0] \n\t" "xor %[addr0], %[addr0], %[addr0] \n\t"
PTR_ADDU "%[pixels], %[pixels], %[line_size] \n\t" PTR_ADDU "%[pixels], %[pixels], %[line_size] \n\t"
".p2align 3 \n\t" ".p2align 3 \n\t"

"1: \n\t" "1: \n\t"
PTR_ADDU "%[addr1], %[pixels], %[addr0] \n\t" PTR_ADDU "%[addr1], %[pixels], %[addr0] \n\t"
"gsldlc1 %[ftmp0], 0x07(%[addr1]) \n\t"
"gsldrc1 %[ftmp0], 0x00(%[addr1]) \n\t"
"gsldlc1 %[ftmp2], 0x08(%[addr1]) \n\t"
"gsldrc1 %[ftmp2], 0x01(%[addr1]) \n\t"
MMI_ULDC1(%[ftmp0], %[addr1], 0x00)
MMI_ULDC1(%[ftmp2], %[addr1], 0x01)
"mov.d %[ftmp1], %[ftmp0] \n\t" "mov.d %[ftmp1], %[ftmp0] \n\t"
"mov.d %[ftmp3], %[ftmp2] \n\t" "mov.d %[ftmp3], %[ftmp2] \n\t"
"punpcklbh %[ftmp0], %[ftmp0], %[ftmp7] \n\t" "punpcklbh %[ftmp0], %[ftmp0], %[ftmp7] \n\t"
@@ -1030,13 +963,11 @@ void ff_put_pixels8_xy2_8_mmi(uint8_t *block, const uint8_t *pixels,
"psrlh %[ftmp4], %[ftmp4], %[ftmp9] \n\t" "psrlh %[ftmp4], %[ftmp4], %[ftmp9] \n\t"
"psrlh %[ftmp5], %[ftmp5], %[ftmp9] \n\t" "psrlh %[ftmp5], %[ftmp5], %[ftmp9] \n\t"
"packushb %[ftmp4], %[ftmp4], %[ftmp5] \n\t" "packushb %[ftmp4], %[ftmp4], %[ftmp5] \n\t"
"gssdxc1 %[ftmp4], 0x00(%[block], %[addr0]) \n\t"
MMI_SDXC1(%[ftmp4], %[block], %[addr0], 0x00)
PTR_ADDU "%[addr0], %[addr0], %[line_size] \n\t" PTR_ADDU "%[addr0], %[addr0], %[line_size] \n\t"
PTR_ADDU "%[addr1], %[pixels], %[addr0] \n\t" PTR_ADDU "%[addr1], %[pixels], %[addr0] \n\t"
"gsldlc1 %[ftmp2], 0x07(%[addr1]) \n\t"
"gsldrc1 %[ftmp2], 0x00(%[addr1]) \n\t"
"gsldlc1 %[ftmp4], 0x08(%[addr1]) \n\t"
"gsldrc1 %[ftmp4], 0x01(%[addr1]) \n\t"
MMI_ULDC1(%[ftmp2], %[addr1], 0x00)
MMI_ULDC1(%[ftmp4], %[addr1], 0x01)
"mov.d %[ftmp3], %[ftmp2] \n\t" "mov.d %[ftmp3], %[ftmp2] \n\t"
"mov.d %[ftmp5], %[ftmp4] \n\t" "mov.d %[ftmp5], %[ftmp4] \n\t"
"punpcklbh %[ftmp2], %[ftmp2], %[ftmp7] \n\t" "punpcklbh %[ftmp2], %[ftmp2], %[ftmp7] \n\t"
@@ -1052,7 +983,7 @@ void ff_put_pixels8_xy2_8_mmi(uint8_t *block, const uint8_t *pixels,
"psrlh %[ftmp0], %[ftmp0], %[ftmp9] \n\t" "psrlh %[ftmp0], %[ftmp0], %[ftmp9] \n\t"
"psrlh %[ftmp1], %[ftmp1], %[ftmp9] \n\t" "psrlh %[ftmp1], %[ftmp1], %[ftmp9] \n\t"
"packushb %[ftmp0], %[ftmp0], %[ftmp1] \n\t" "packushb %[ftmp0], %[ftmp0], %[ftmp1] \n\t"
"gssdxc1 %[ftmp0], 0x00(%[block], %[addr0]) \n\t"
MMI_SDXC1(%[ftmp0], %[block], %[addr0], 0x00)
PTR_ADDU "%[addr0], %[addr0], %[line_size] \n\t" PTR_ADDU "%[addr0], %[addr0], %[line_size] \n\t"
PTR_ADDU "%[h], %[h], -0x02 \n\t" PTR_ADDU "%[h], %[h], -0x02 \n\t"
"bnez %[h], 1b \n\t" "bnez %[h], 1b \n\t"
@@ -1061,6 +992,8 @@ void ff_put_pixels8_xy2_8_mmi(uint8_t *block, const uint8_t *pixels,
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]), [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]), [ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
[ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]), [ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]),
RESTRICT_ASM_ALL64
RESTRICT_ASM_ADDRT
[addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]), [addr0]"=&r"(addr[0]), [addr1]"=&r"(addr[1]),
[h]"+&r"(h), [pixels]"+&r"(pixels) [h]"+&r"(h), [pixels]"+&r"(pixels)
: [block]"r"(block), [line_size]"r"((mips_reg)line_size) : [block]"r"(block), [line_size]"r"((mips_reg)line_size)


+ 73
- 57
libavcodec/mips/idctdsp_mmi.c View File

@@ -23,36 +23,40 @@


#include "idctdsp_mips.h" #include "idctdsp_mips.h"
#include "constants.h" #include "constants.h"
#include "libavutil/mips/asmdefs.h"
#include "libavutil/mips/mmiutils.h"


void ff_put_pixels_clamped_mmi(const int16_t *block, void ff_put_pixels_clamped_mmi(const int16_t *block,
uint8_t *av_restrict pixels, ptrdiff_t line_size) uint8_t *av_restrict pixels, ptrdiff_t line_size)
{ {
double ftmp[8]; double ftmp[8];
mips_reg addr[1]; mips_reg addr[1];
DECLARE_VAR_ALL64;
DECLARE_VAR_ADDRT;


__asm__ volatile ( __asm__ volatile (
"ldc1 %[ftmp0], 0x00(%[block]) \n\t"
"ldc1 %[ftmp1], 0x08(%[block]) \n\t"
"ldc1 %[ftmp2], 0x10(%[block]) \n\t"
"ldc1 %[ftmp3], 0x18(%[block]) \n\t"
"ldc1 %[ftmp4], 0x20(%[block]) \n\t"
"ldc1 %[ftmp5], 0x28(%[block]) \n\t"
"ldc1 %[ftmp6], 0x30(%[block]) \n\t"
"ldc1 %[ftmp7], 0x38(%[block]) \n\t"
MMI_LDC1(%[ftmp0], %[block], 0x00)
MMI_LDC1(%[ftmp1], %[block], 0x08)
MMI_LDC1(%[ftmp2], %[block], 0x10)
MMI_LDC1(%[ftmp3], %[block], 0x18)
MMI_LDC1(%[ftmp4], %[block], 0x20)
MMI_LDC1(%[ftmp5], %[block], 0x28)
MMI_LDC1(%[ftmp6], %[block], 0x30)
MMI_LDC1(%[ftmp7], %[block], 0x38)
PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t" PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t"
"packushb %[ftmp0], %[ftmp0], %[ftmp1] \n\t" "packushb %[ftmp0], %[ftmp0], %[ftmp1] \n\t"
"packushb %[ftmp2], %[ftmp2], %[ftmp3] \n\t" "packushb %[ftmp2], %[ftmp2], %[ftmp3] \n\t"
"packushb %[ftmp4], %[ftmp4], %[ftmp5] \n\t" "packushb %[ftmp4], %[ftmp4], %[ftmp5] \n\t"
"packushb %[ftmp6], %[ftmp6], %[ftmp7] \n\t" "packushb %[ftmp6], %[ftmp6], %[ftmp7] \n\t"
"sdc1 %[ftmp0], 0x00(%[pixels]) \n\t"
"sdc1 %[ftmp2], 0x00(%[addr0]) \n\t"
"gssdxc1 %[ftmp4], 0x00(%[addr0], %[line_size]) \n\t"
"gssdxc1 %[ftmp6], 0x00(%[pixels], %[line_sizex3]) \n\t"
MMI_SDC1(%[ftmp0], %[pixels], 0x00)
MMI_SDC1(%[ftmp2], %[addr0], 0x00)
MMI_SDXC1(%[ftmp4], %[addr0], %[line_size], 0x00)
MMI_SDXC1(%[ftmp6], %[pixels], %[line_sizex3], 0x00)
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]), [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]), [ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
RESTRICT_ASM_ALL64
RESTRICT_ASM_ADDRT
[addr0]"=&r"(addr[0]), [addr0]"=&r"(addr[0]),
[pixels]"+&r"(pixels) [pixels]"+&r"(pixels)
: [line_size]"r"((mips_reg)line_size), : [line_size]"r"((mips_reg)line_size),
@@ -65,27 +69,29 @@ void ff_put_pixels_clamped_mmi(const int16_t *block,
block += 32; block += 32;


__asm__ volatile ( __asm__ volatile (
"ldc1 %[ftmp0], 0x00(%[block]) \n\t"
"ldc1 %[ftmp1], 0x08(%[block]) \n\t"
"ldc1 %[ftmp2], 0x10(%[block]) \n\t"
"ldc1 %[ftmp3], 0x18(%[block]) \n\t"
"ldc1 %[ftmp4], 0x20(%[block]) \n\t"
"ldc1 %[ftmp5], 0x28(%[block]) \n\t"
"ldc1 %[ftmp6], 0x30(%[block]) \n\t"
"ldc1 %[ftmp7], 0x38(%[block]) \n\t"
MMI_LDC1(%[ftmp0], %[block], 0x00)
MMI_LDC1(%[ftmp1], %[block], 0x08)
MMI_LDC1(%[ftmp2], %[block], 0x10)
MMI_LDC1(%[ftmp3], %[block], 0x18)
MMI_LDC1(%[ftmp4], %[block], 0x20)
MMI_LDC1(%[ftmp5], %[block], 0x28)
MMI_LDC1(%[ftmp6], %[block], 0x30)
MMI_LDC1(%[ftmp7], %[block], 0x38)
PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t" PTR_ADDU "%[addr0], %[pixels], %[line_size] \n\t"
"packushb %[ftmp0], %[ftmp0], %[ftmp1] \n\t" "packushb %[ftmp0], %[ftmp0], %[ftmp1] \n\t"
"packushb %[ftmp2], %[ftmp2], %[ftmp3] \n\t" "packushb %[ftmp2], %[ftmp2], %[ftmp3] \n\t"
"packushb %[ftmp4], %[ftmp4], %[ftmp5] \n\t" "packushb %[ftmp4], %[ftmp4], %[ftmp5] \n\t"
"packushb %[ftmp6], %[ftmp6], %[ftmp7] \n\t" "packushb %[ftmp6], %[ftmp6], %[ftmp7] \n\t"
"sdc1 %[ftmp0], 0x00(%[pixels]) \n\t"
"sdc1 %[ftmp2], 0x00(%[addr0]) \n\t"
"gssdxc1 %[ftmp4], 0x00(%[addr0], %[line_size]) \n\t"
"gssdxc1 %[ftmp6], 0x00(%[pixels], %[line_sizex3]) \n\t"
MMI_SDC1(%[ftmp0], %[pixels], 0x00)
MMI_SDC1(%[ftmp2], %[addr0], 0x00)
MMI_SDXC1(%[ftmp4], %[addr0], %[line_size], 0x00)
MMI_SDXC1(%[ftmp6], %[pixels], %[line_sizex3], 0x00)
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]), [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]), [ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
RESTRICT_ASM_ALL64
RESTRICT_ASM_ADDRT
[addr0]"=&r"(addr[0]), [addr0]"=&r"(addr[0]),
[pixels]"+&r"(pixels) [pixels]"+&r"(pixels)
: [line_size]"r"((mips_reg)line_size), : [line_size]"r"((mips_reg)line_size),
@@ -102,56 +108,60 @@ void ff_put_signed_pixels_clamped_mmi(const int16_t *block,
int64_t line_skip3 = 0; int64_t line_skip3 = 0;
double ftmp[5]; double ftmp[5];
mips_reg addr[1]; mips_reg addr[1];
DECLARE_VAR_ALL64;
DECLARE_VAR_ADDRT;


__asm__ volatile ( __asm__ volatile (
PTR_ADDU "%[line_skip3], %[line_skip], %[line_skip] \n\t" PTR_ADDU "%[line_skip3], %[line_skip], %[line_skip] \n\t"
"ldc1 %[ftmp1], 0x00(%[block]) \n\t"
"ldc1 %[ftmp0], 0x08(%[block]) \n\t"
MMI_LDC1(%[ftmp1], %[block], 0x00)
MMI_LDC1(%[ftmp0], %[block], 0x08)
"packsshb %[ftmp1], %[ftmp1], %[ftmp0] \n\t" "packsshb %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
"ldc1 %[ftmp2], 0x10(%[block]) \n\t"
"ldc1 %[ftmp0], 0x18(%[block]) \n\t"
MMI_LDC1(%[ftmp2], %[block], 0x10)
MMI_LDC1(%[ftmp0], %[block], 0x18)
"packsshb %[ftmp2], %[ftmp2], %[ftmp0] \n\t" "packsshb %[ftmp2], %[ftmp2], %[ftmp0] \n\t"
"ldc1 %[ftmp3], 0x20(%[block]) \n\t"
"ldc1 %[ftmp0], 0x28(%[block]) \n\t"
MMI_LDC1(%[ftmp3], %[block], 0x20)
MMI_LDC1(%[ftmp0], %[block], 0x28)
"packsshb %[ftmp3], %[ftmp3], %[ftmp0] \n\t" "packsshb %[ftmp3], %[ftmp3], %[ftmp0] \n\t"
"ldc1 %[ftmp4], 48(%[block]) \n\t"
"ldc1 %[ftmp0], 56(%[block]) \n\t"
MMI_LDC1(%[ftmp4], %[block], 0x30)
MMI_LDC1(%[ftmp0], %[block], 0x38)
"packsshb %[ftmp4], %[ftmp4], %[ftmp0] \n\t" "packsshb %[ftmp4], %[ftmp4], %[ftmp0] \n\t"
"paddb %[ftmp1], %[ftmp1], %[ff_pb_80] \n\t" "paddb %[ftmp1], %[ftmp1], %[ff_pb_80] \n\t"
"paddb %[ftmp2], %[ftmp2], %[ff_pb_80] \n\t" "paddb %[ftmp2], %[ftmp2], %[ff_pb_80] \n\t"
"paddb %[ftmp3], %[ftmp3], %[ff_pb_80] \n\t" "paddb %[ftmp3], %[ftmp3], %[ff_pb_80] \n\t"
"paddb %[ftmp4], %[ftmp4], %[ff_pb_80] \n\t" "paddb %[ftmp4], %[ftmp4], %[ff_pb_80] \n\t"
"sdc1 %[ftmp1], 0x00(%[pixels]) \n\t"
"gssdxc1 %[ftmp2], 0x00(%[pixels], %[line_skip]) \n\t"
"gssdxc1 %[ftmp3], 0x00(%[pixels], %[line_skip3]) \n\t"
MMI_SDC1(%[ftmp1], %[pixels], 0x00)
MMI_SDXC1(%[ftmp2], %[pixels], %[line_skip], 0x00)
MMI_SDXC1(%[ftmp3], %[pixels], %[line_skip3], 0x00)
PTR_ADDU "%[line_skip3], %[line_skip3], %[line_skip] \n\t" PTR_ADDU "%[line_skip3], %[line_skip3], %[line_skip] \n\t"
"gssdxc1 %[ftmp4], 0x00(%[pixels], %[line_skip3]) \n\t"
MMI_SDXC1(%[ftmp4], %[pixels], %[line_skip3], 0x00)
PTR_ADDU "%[addr0], %[line_skip3], %[line_skip] \n\t" PTR_ADDU "%[addr0], %[line_skip3], %[line_skip] \n\t"
PTR_ADDU "%[pixels], %[pixels], %[addr0] \n\t" PTR_ADDU "%[pixels], %[pixels], %[addr0] \n\t"
"ldc1 %[ftmp1], 0x40(%[block]) \n\t"
"ldc1 %[ftmp0], 0x48(%[block]) \n\t"
MMI_LDC1(%[ftmp1], %[block], 0x40)
MMI_LDC1(%[ftmp0], %[block], 0x48)
"packsshb %[ftmp1], %[ftmp1], %[ftmp0] \n\t" "packsshb %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
"ldc1 %[ftmp2], 0x50(%[block]) \n\t"
"ldc1 %[ftmp0], 0x58(%[block]) \n\t"
MMI_LDC1(%[ftmp2], %[block], 0x50)
MMI_LDC1(%[ftmp0], %[block], 0x58)
"packsshb %[ftmp2], %[ftmp2], %[ftmp0] \n\t" "packsshb %[ftmp2], %[ftmp2], %[ftmp0] \n\t"
"ldc1 %[ftmp3], 0x60(%[block]) \n\t"
"ldc1 %[ftmp0], 0x68(%[block]) \n\t"
MMI_LDC1(%[ftmp3], %[block], 0x60)
MMI_LDC1(%[ftmp0], %[block], 0x68)
"packsshb %[ftmp3], %[ftmp3], %[ftmp0] \n\t" "packsshb %[ftmp3], %[ftmp3], %[ftmp0] \n\t"
"ldc1 %[ftmp4], 0x70(%[block]) \n\t"
"ldc1 %[ftmp0], 0x78(%[block]) \n\t"
MMI_LDC1(%[ftmp4], %[block], 0x70)
MMI_LDC1(%[ftmp0], %[block], 0x78)
"packsshb %[ftmp4], %[ftmp4], %[ftmp0] \n\t" "packsshb %[ftmp4], %[ftmp4], %[ftmp0] \n\t"
"paddb %[ftmp1], %[ftmp1], %[ff_pb_80] \n\t" "paddb %[ftmp1], %[ftmp1], %[ff_pb_80] \n\t"
"paddb %[ftmp2], %[ftmp2], %[ff_pb_80] \n\t" "paddb %[ftmp2], %[ftmp2], %[ff_pb_80] \n\t"
"paddb %[ftmp3], %[ftmp3], %[ff_pb_80] \n\t" "paddb %[ftmp3], %[ftmp3], %[ff_pb_80] \n\t"
"paddb %[ftmp4], %[ftmp4], %[ff_pb_80] \n\t" "paddb %[ftmp4], %[ftmp4], %[ff_pb_80] \n\t"
"sdc1 %[ftmp1], 0x00(%[pixels]) \n\t"
"gssdxc1 %[ftmp2], 0x00(%[pixels], %[line_skip]) \n\t"
MMI_SDC1(%[ftmp1], %[pixels], 0x00)
MMI_SDXC1(%[ftmp2], %[pixels], %[line_skip], 0x00)
PTR_ADDU "%[addr0], %[line_skip], %[line_skip] \n\t" PTR_ADDU "%[addr0], %[line_skip], %[line_skip] \n\t"
"gssdxc1 %[ftmp3], 0x00(%[pixels], %[addr0]) \n\t"
"gssdxc1 %[ftmp4], 0x00(%[pixels], %[line_skip3]) \n\t"
MMI_SDXC1(%[ftmp3], %[pixels], %[addr0], 0x00)
MMI_SDXC1(%[ftmp4], %[pixels], %[line_skip3], 0x00)
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
[ftmp4]"=&f"(ftmp[4]), [ftmp4]"=&f"(ftmp[4]),
RESTRICT_ASM_ALL64
RESTRICT_ASM_ADDRT
[addr0]"=&r"(addr[0]), [addr0]"=&r"(addr[0]),
[pixels]"+&r"(pixels), [line_skip3]"+&r"(line_skip3) [pixels]"+&r"(pixels), [line_skip3]"+&r"(line_skip3)
: [block]"r"(block), : [block]"r"(block),
@@ -166,17 +176,20 @@ void ff_add_pixels_clamped_mmi(const int16_t *block,
{ {
double ftmp[8]; double ftmp[8];
uint64_t tmp[1]; uint64_t tmp[1];
mips_reg addr[1];
DECLARE_VAR_ALL64;
DECLARE_VAR_ADDRT;


__asm__ volatile ( __asm__ volatile (
"li %[tmp0], 0x04 \n\t" "li %[tmp0], 0x04 \n\t"
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"1: \n\t" "1: \n\t"
"ldc1 %[ftmp1], 0x00(%[block]) \n\t"
"ldc1 %[ftmp2], 0x08(%[block]) \n\t"
"ldc1 %[ftmp3], 0x10(%[block]) \n\t"
"ldc1 %[ftmp4], 0x18(%[block]) \n\t"
"ldc1 %[ftmp5], 0x00(%[pixels]) \n\t"
"gsldxc1 %[ftmp6], 0x00(%[pixels], %[line_size]) \n\t"
MMI_LDC1(%[ftmp1], %[block], 0x00)
MMI_LDC1(%[ftmp2], %[block], 0x08)
MMI_LDC1(%[ftmp3], %[block], 0x10)
MMI_LDC1(%[ftmp4], %[block], 0x18)
MMI_LDC1(%[ftmp5], %[pixels], 0x00)
MMI_LDXC1(%[ftmp6], %[pixels], %[line_size], 0x00)
"mov.d %[ftmp7], %[ftmp5] \n\t" "mov.d %[ftmp7], %[ftmp5] \n\t"
"punpcklbh %[ftmp5], %[ftmp5], %[ftmp0] \n\t" "punpcklbh %[ftmp5], %[ftmp5], %[ftmp0] \n\t"
"punpckhbh %[ftmp7], %[ftmp7], %[ftmp0] \n\t" "punpckhbh %[ftmp7], %[ftmp7], %[ftmp0] \n\t"
@@ -189,8 +202,8 @@ void ff_add_pixels_clamped_mmi(const int16_t *block,
"paddh %[ftmp4], %[ftmp4], %[ftmp7] \n\t" "paddh %[ftmp4], %[ftmp4], %[ftmp7] \n\t"
"packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t" "packushb %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
"packushb %[ftmp3], %[ftmp3], %[ftmp4] \n\t" "packushb %[ftmp3], %[ftmp3], %[ftmp4] \n\t"
"sdc1 %[ftmp1], 0x00(%[pixels]) \n\t"
"gssdxc1 %[ftmp3], 0x00(%[pixels], %[line_size]) \n\t"
MMI_SDC1(%[ftmp1], %[pixels], 0x00)
MMI_SDXC1(%[ftmp3], %[pixels], %[line_size], 0x00)
"addi %[tmp0], %[tmp0], -0x01 \n\t" "addi %[tmp0], %[tmp0], -0x01 \n\t"
PTR_ADDIU "%[block], %[block], 0x20 \n\t" PTR_ADDIU "%[block], %[block], 0x20 \n\t"
PTR_ADDU "%[pixels], %[pixels], %[line_size] \n\t" PTR_ADDU "%[pixels], %[pixels], %[line_size] \n\t"
@@ -201,6 +214,9 @@ void ff_add_pixels_clamped_mmi(const int16_t *block,
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]), [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]), [ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
[tmp0]"=&r"(tmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_ALL64
RESTRICT_ASM_ADDRT
[addr0]"=&r"(addr[0]),
[pixels]"+&r"(pixels), [block]"+&r"(block) [pixels]"+&r"(pixels), [block]"+&r"(block)
: [line_size]"r"((mips_reg)line_size) : [line_size]"r"((mips_reg)line_size)
: "memory" : "memory"


+ 63
- 49
libavcodec/mips/mpegvideo_mmi.c View File

@@ -23,7 +23,7 @@
*/ */


#include "mpegvideo_mips.h" #include "mpegvideo_mips.h"
#include "libavutil/mips/asmdefs.h"
#include "libavutil/mips/mmiutils.h"


void ff_dct_unquantize_h263_intra_mmi(MpegEncContext *s, int16_t *block, void ff_dct_unquantize_h263_intra_mmi(MpegEncContext *s, int16_t *block,
int n, int qscale) int n, int qscale)
@@ -31,6 +31,7 @@ void ff_dct_unquantize_h263_intra_mmi(MpegEncContext *s, int16_t *block,
int64_t level, qmul, qadd, nCoeffs; int64_t level, qmul, qadd, nCoeffs;
double ftmp[6]; double ftmp[6];
mips_reg addr[1]; mips_reg addr[1];
DECLARE_VAR_ALL64;


qmul = qscale << 1; qmul = qscale << 1;
av_assert2(s->block_last_index[n]>=0 || s->h263_aic); av_assert2(s->block_last_index[n]>=0 || s->h263_aic);
@@ -60,12 +61,11 @@ void ff_dct_unquantize_h263_intra_mmi(MpegEncContext *s, int16_t *block,
"psubh %[ftmp0], %[ftmp0], %[qadd] \n\t" "psubh %[ftmp0], %[ftmp0], %[qadd] \n\t"
"xor %[ftmp5], %[ftmp5], %[ftmp5] \n\t" "xor %[ftmp5], %[ftmp5], %[ftmp5] \n\t"
".p2align 4 \n\t" ".p2align 4 \n\t"

"1: \n\t" "1: \n\t"
PTR_ADDU "%[addr0], %[block], %[nCoeffs] \n\t" PTR_ADDU "%[addr0], %[block], %[nCoeffs] \n\t"
"gsldlc1 %[ftmp1], 0x07(%[addr0]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[addr0]) \n\t"
"gsldlc1 %[ftmp2], 0x0f(%[addr0]) \n\t"
"gsldrc1 %[ftmp2], 0x08(%[addr0]) \n\t"
MMI_LDC1(%[ftmp1], %[addr0], 0x00)
MMI_LDC1(%[ftmp2], %[addr0], 0x08)
"mov.d %[ftmp3], %[ftmp1] \n\t" "mov.d %[ftmp3], %[ftmp1] \n\t"
"mov.d %[ftmp4], %[ftmp2] \n\t" "mov.d %[ftmp4], %[ftmp2] \n\t"
"pmullh %[ftmp1], %[ftmp1], %[qmul] \n\t" "pmullh %[ftmp1], %[ftmp1], %[qmul] \n\t"
@@ -83,14 +83,13 @@ void ff_dct_unquantize_h263_intra_mmi(MpegEncContext *s, int16_t *block,
"pandn %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "pandn %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
"pandn %[ftmp2], %[ftmp2], %[ftmp4] \n\t" "pandn %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
PTR_ADDIU "%[nCoeffs], %[nCoeffs], 0x10 \n\t" PTR_ADDIU "%[nCoeffs], %[nCoeffs], 0x10 \n\t"
"gssdlc1 %[ftmp1], 0x07(%[addr0]) \n\t"
"gssdrc1 %[ftmp1], 0x00(%[addr0]) \n\t"
"gssdlc1 %[ftmp2], 0x0f(%[addr0]) \n\t"
"gssdrc1 %[ftmp2], 0x08(%[addr0]) \n\t"
MMI_SDC1(%[ftmp1], %[addr0], 0x00)
MMI_SDC1(%[ftmp2], %[addr0], 0x08)
"blez %[nCoeffs], 1b \n\t" "blez %[nCoeffs], 1b \n\t"
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]), [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
RESTRICT_ASM_ALL64
[addr0]"=&r"(addr[0]) [addr0]"=&r"(addr[0])
: [block]"r"((mips_reg)(block+nCoeffs)), : [block]"r"((mips_reg)(block+nCoeffs)),
[nCoeffs]"r"((mips_reg)(2*(-nCoeffs))), [nCoeffs]"r"((mips_reg)(2*(-nCoeffs))),
@@ -107,6 +106,7 @@ void ff_dct_unquantize_h263_inter_mmi(MpegEncContext *s, int16_t *block,
int64_t qmul, qadd, nCoeffs; int64_t qmul, qadd, nCoeffs;
double ftmp[6]; double ftmp[6];
mips_reg addr[1]; mips_reg addr[1];
DECLARE_VAR_ALL64;


qmul = qscale << 1; qmul = qscale << 1;
qadd = (qscale - 1) | 1; qadd = (qscale - 1) | 1;
@@ -124,10 +124,8 @@ void ff_dct_unquantize_h263_inter_mmi(MpegEncContext *s, int16_t *block,
".p2align 4 \n\t" ".p2align 4 \n\t"
"1: \n\t" "1: \n\t"
PTR_ADDU "%[addr0], %[block], %[nCoeffs] \n\t" PTR_ADDU "%[addr0], %[block], %[nCoeffs] \n\t"
"gsldlc1 %[ftmp1], 0x07(%[addr0]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[addr0]) \n\t"
"gsldlc1 %[ftmp2], 0x0f(%[addr0]) \n\t"
"gsldrc1 %[ftmp2], 0x08(%[addr0]) \n\t"
MMI_LDC1(%[ftmp1], %[addr0], 0x00)
MMI_LDC1(%[ftmp2], %[addr0], 0x08)
"mov.d %[ftmp3], %[ftmp1] \n\t" "mov.d %[ftmp3], %[ftmp1] \n\t"
"mov.d %[ftmp4], %[ftmp2] \n\t" "mov.d %[ftmp4], %[ftmp2] \n\t"
"pmullh %[ftmp1], %[ftmp1], %[qmul] \n\t" "pmullh %[ftmp1], %[ftmp1], %[qmul] \n\t"
@@ -145,14 +143,13 @@ void ff_dct_unquantize_h263_inter_mmi(MpegEncContext *s, int16_t *block,
"pandn %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "pandn %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
"pandn %[ftmp2], %[ftmp2], %[ftmp4] \n\t" "pandn %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
PTR_ADDIU "%[nCoeffs], %[nCoeffs], 0x10 \n\t" PTR_ADDIU "%[nCoeffs], %[nCoeffs], 0x10 \n\t"
"gssdlc1 %[ftmp1], 0x07(%[addr0]) \n\t"
"gssdrc1 %[ftmp1], 0x00(%[addr0]) \n\t"
"gssdlc1 %[ftmp2], 0x0f(%[addr0]) \n\t"
"gssdrc1 %[ftmp2], 0x08(%[addr0]) \n\t"
MMI_SDC1(%[ftmp1], %[addr0], 0x00)
MMI_SDC1(%[ftmp2], %[addr0], 0x08)
"blez %[nCoeffs], 1b \n\t" "blez %[nCoeffs], 1b \n\t"
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]), [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
RESTRICT_ASM_ALL64
[addr0]"=&r"(addr[0]) [addr0]"=&r"(addr[0])
: [block]"r"((mips_reg)(block+nCoeffs)), : [block]"r"((mips_reg)(block+nCoeffs)),
[nCoeffs]"r"((mips_reg)(2*(-nCoeffs))), [nCoeffs]"r"((mips_reg)(2*(-nCoeffs))),
@@ -170,6 +167,8 @@ void ff_dct_unquantize_mpeg1_intra_mmi(MpegEncContext *s, int16_t *block,
double ftmp[10]; double ftmp[10];
uint64_t tmp[1]; uint64_t tmp[1];
mips_reg addr[1]; mips_reg addr[1];
DECLARE_VAR_ALL64;
DECLARE_VAR_ADDRT;


av_assert2(s->block_last_index[n]>=0); av_assert2(s->block_last_index[n]>=0);
nCoeffs = s->intra_scantable.raster_end[s->block_last_index[n]] + 1; nCoeffs = s->intra_scantable.raster_end[s->block_last_index[n]] + 1;
@@ -192,13 +191,14 @@ void ff_dct_unquantize_mpeg1_intra_mmi(MpegEncContext *s, int16_t *block,
"packsswh %[ftmp1], %[ftmp1], %[ftmp1] \n\t" "packsswh %[ftmp1], %[ftmp1], %[ftmp1] \n\t"
"or %[addr0], %[nCoeffs], $0 \n\t" "or %[addr0], %[nCoeffs], $0 \n\t"
".p2align 4 \n\t" ".p2align 4 \n\t"

"1: \n\t" "1: \n\t"
"gsldxc1 %[ftmp2], 0x00(%[addr0], %[block]) \n\t"
"gsldxc1 %[ftmp3], 0x08(%[addr0], %[block]) \n\t"
MMI_LDXC1(%[ftmp2], %[addr0], %[block], 0x00)
MMI_LDXC1(%[ftmp3], %[addr0], %[block], 0x08)
"mov.d %[ftmp4], %[ftmp2] \n\t" "mov.d %[ftmp4], %[ftmp2] \n\t"
"mov.d %[ftmp5], %[ftmp3] \n\t" "mov.d %[ftmp5], %[ftmp3] \n\t"
"gsldxc1 %[ftmp6], 0x00(%[addr0], %[quant]) \n\t"
"gsldxc1 %[ftmp7], 0x08(%[addr0], %[quant]) \n\t"
MMI_LDXC1(%[ftmp6], %[addr0], %[quant], 0x00)
MMI_LDXC1(%[ftmp7], %[addr0], %[quant], 0x08)
"pmullh %[ftmp6], %[ftmp6], %[ftmp1] \n\t" "pmullh %[ftmp6], %[ftmp6], %[ftmp1] \n\t"
"pmullh %[ftmp7], %[ftmp7], %[ftmp1] \n\t" "pmullh %[ftmp7], %[ftmp7], %[ftmp1] \n\t"
"xor %[ftmp8], %[ftmp8], %[ftmp8] \n\t" "xor %[ftmp8], %[ftmp8], %[ftmp8] \n\t"
@@ -229,8 +229,8 @@ void ff_dct_unquantize_mpeg1_intra_mmi(MpegEncContext *s, int16_t *block,
"psubh %[ftmp3], %[ftmp3], %[ftmp9] \n\t" "psubh %[ftmp3], %[ftmp3], %[ftmp9] \n\t"
"pandn %[ftmp6], %[ftmp6], %[ftmp2] \n\t" "pandn %[ftmp6], %[ftmp6], %[ftmp2] \n\t"
"pandn %[ftmp7], %[ftmp7], %[ftmp3] \n\t" "pandn %[ftmp7], %[ftmp7], %[ftmp3] \n\t"
"gssdxc1 %[ftmp6], 0x00(%[addr0], %[block]) \n\t"
"gssdxc1 %[ftmp7], 0x08(%[addr0], %[block]) \n\t"
MMI_SDXC1(%[ftmp6], %[addr0], %[block], 0x00)
MMI_SDXC1(%[ftmp7], %[addr0], %[block], 0x08)
PTR_ADDIU "%[addr0], %[addr0], 0x10 \n\t" PTR_ADDIU "%[addr0], %[addr0], 0x10 \n\t"
"bltz %[addr0], 1b \n\t" "bltz %[addr0], 1b \n\t"
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
@@ -239,6 +239,8 @@ void ff_dct_unquantize_mpeg1_intra_mmi(MpegEncContext *s, int16_t *block,
[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]), [ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
[ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]), [ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]),
[tmp0]"=&r"(tmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_ALL64
RESTRICT_ASM_ADDRT
[addr0]"=&r"(addr[0]) [addr0]"=&r"(addr[0])
: [block]"r"((mips_reg)(block+nCoeffs)), : [block]"r"((mips_reg)(block+nCoeffs)),
[quant]"r"((mips_reg)(quant_matrix+nCoeffs)), [quant]"r"((mips_reg)(quant_matrix+nCoeffs)),
@@ -258,6 +260,8 @@ void ff_dct_unquantize_mpeg1_inter_mmi(MpegEncContext *s, int16_t *block,
double ftmp[10]; double ftmp[10];
uint64_t tmp[1]; uint64_t tmp[1];
mips_reg addr[1]; mips_reg addr[1];
DECLARE_VAR_ALL64;
DECLARE_VAR_ADDRT;


av_assert2(s->block_last_index[n] >= 0); av_assert2(s->block_last_index[n] >= 0);
nCoeffs = s->intra_scantable.raster_end[s->block_last_index[n]] + 1; nCoeffs = s->intra_scantable.raster_end[s->block_last_index[n]] + 1;
@@ -273,13 +277,14 @@ void ff_dct_unquantize_mpeg1_inter_mmi(MpegEncContext *s, int16_t *block,
"packsswh %[ftmp1], %[ftmp1], %[ftmp1] \n\t" "packsswh %[ftmp1], %[ftmp1], %[ftmp1] \n\t"
"or %[addr0], %[nCoeffs], $0 \n\t" "or %[addr0], %[nCoeffs], $0 \n\t"
".p2align 4 \n\t" ".p2align 4 \n\t"

"1: \n\t" "1: \n\t"
"gsldxc1 %[ftmp2], 0x00(%[addr0], %[block]) \n\t"
"gsldxc1 %[ftmp3], 0x08(%[addr0], %[block]) \n\t"
MMI_LDXC1(%[ftmp2], %[addr0], %[block], 0x00)
MMI_LDXC1(%[ftmp3], %[addr0], %[block], 0x08)
"mov.d %[ftmp4], %[ftmp2] \n\t" "mov.d %[ftmp4], %[ftmp2] \n\t"
"mov.d %[ftmp5], %[ftmp3] \n\t" "mov.d %[ftmp5], %[ftmp3] \n\t"
"gsldxc1 %[ftmp6], 0x00(%[addr0], %[quant]) \n\t"
"gsldxc1 %[ftmp7], 0x08(%[addr0], %[quant]) \n\t"
MMI_LDXC1(%[ftmp6], %[addr0], %[quant], 0x00)
MMI_LDXC1(%[ftmp7], %[addr0], %[quant], 0x08)
"pmullh %[ftmp6], %[ftmp6], %[ftmp1] \n\t" "pmullh %[ftmp6], %[ftmp6], %[ftmp1] \n\t"
"pmullh %[ftmp7], %[ftmp7], %[ftmp1] \n\t" "pmullh %[ftmp7], %[ftmp7], %[ftmp1] \n\t"
"xor %[ftmp8], %[ftmp8], %[ftmp8] \n\t" "xor %[ftmp8], %[ftmp8], %[ftmp8] \n\t"
@@ -314,8 +319,8 @@ void ff_dct_unquantize_mpeg1_inter_mmi(MpegEncContext *s, int16_t *block,
"psubh %[ftmp3], %[ftmp3], %[ftmp9] \n\t" "psubh %[ftmp3], %[ftmp3], %[ftmp9] \n\t"
"pandn %[ftmp6], %[ftmp6], %[ftmp2] \n\t" "pandn %[ftmp6], %[ftmp6], %[ftmp2] \n\t"
"pandn %[ftmp7], %[ftmp7], %[ftmp3] \n\t" "pandn %[ftmp7], %[ftmp7], %[ftmp3] \n\t"
"gssdxc1 %[ftmp6], 0x00(%[addr0], %[block]) \n\t"
"gssdxc1 %[ftmp7], 0x08(%[addr0], %[block]) \n\t"
MMI_SDXC1(%[ftmp6], %[addr0], %[block], 0x00)
MMI_SDXC1(%[ftmp7], %[addr0], %[block], 0x08)
PTR_ADDIU "%[addr0], %[addr0], 0x10 \n\t" PTR_ADDIU "%[addr0], %[addr0], 0x10 \n\t"
"bltz %[addr0], 1b \n\t" "bltz %[addr0], 1b \n\t"
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
@@ -324,6 +329,8 @@ void ff_dct_unquantize_mpeg1_inter_mmi(MpegEncContext *s, int16_t *block,
[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]), [ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
[ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]), [ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]),
[tmp0]"=&r"(tmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_ALL64
RESTRICT_ASM_ADDRT
[addr0]"=&r"(addr[0]) [addr0]"=&r"(addr[0])
: [block]"r"((mips_reg)(block+nCoeffs)), : [block]"r"((mips_reg)(block+nCoeffs)),
[quant]"r"((mips_reg)(quant_matrix+nCoeffs)), [quant]"r"((mips_reg)(quant_matrix+nCoeffs)),
@@ -342,6 +349,8 @@ void ff_dct_unquantize_mpeg2_intra_mmi(MpegEncContext *s, int16_t *block,
double ftmp[10]; double ftmp[10];
uint64_t tmp[1]; uint64_t tmp[1];
mips_reg addr[1]; mips_reg addr[1];
DECLARE_VAR_ALL64;
DECLARE_VAR_ADDRT;


assert(s->block_last_index[n]>=0); assert(s->block_last_index[n]>=0);


@@ -367,13 +376,14 @@ void ff_dct_unquantize_mpeg2_intra_mmi(MpegEncContext *s, int16_t *block,
"packsswh %[ftmp9], %[ftmp9], %[ftmp9] \n\t" "packsswh %[ftmp9], %[ftmp9], %[ftmp9] \n\t"
"or %[addr0], %[nCoeffs], $0 \n\t" "or %[addr0], %[nCoeffs], $0 \n\t"
".p2align 4 \n\t" ".p2align 4 \n\t"

"1: \n\t" "1: \n\t"
"gsldxc1 %[ftmp1], 0x00(%[addr0], %[block]) \n\t"
"gsldxc1 %[ftmp2], 0x08(%[addr0], %[block]) \n\t"
MMI_LDXC1(%[ftmp1], %[addr0], %[block], 0x00)
MMI_LDXC1(%[ftmp2], %[addr0], %[block], 0x08)
"mov.d %[ftmp3], %[ftmp1] \n\t" "mov.d %[ftmp3], %[ftmp1] \n\t"
"mov.d %[ftmp4], %[ftmp2] \n\t" "mov.d %[ftmp4], %[ftmp2] \n\t"
"gsldxc1 %[ftmp5], 0x00(%[addr0], %[quant]) \n\t"
"gsldxc1 %[ftmp6], 0x00(%[addr0], %[quant]) \n\t"
MMI_LDXC1(%[ftmp5], %[addr0], %[quant], 0x00)
MMI_LDXC1(%[ftmp6], %[addr0], %[quant], 0x08)
"pmullh %[ftmp5], %[ftmp5], %[ftmp9] \n\t" "pmullh %[ftmp5], %[ftmp5], %[ftmp9] \n\t"
"pmullh %[ftmp6], %[ftmp6], %[ftmp9] \n\t" "pmullh %[ftmp6], %[ftmp6], %[ftmp9] \n\t"
"xor %[ftmp7], %[ftmp7], %[ftmp7] \n\t" "xor %[ftmp7], %[ftmp7], %[ftmp7] \n\t"
@@ -401,8 +411,8 @@ void ff_dct_unquantize_mpeg2_intra_mmi(MpegEncContext *s, int16_t *block,
"pandn %[ftmp5], %[ftmp5], %[ftmp1] \n\t" "pandn %[ftmp5], %[ftmp5], %[ftmp1] \n\t"
"pandn %[ftmp6], %[ftmp6], %[ftmp2] \n\t" "pandn %[ftmp6], %[ftmp6], %[ftmp2] \n\t"
PTR_ADDIU "%[addr0], %[addr0], 0x10 \n\t" PTR_ADDIU "%[addr0], %[addr0], 0x10 \n\t"
"gssdxc1 %[ftmp5], 0x00(%[addr0], %[block]) \n\t"
"gssdxc1 %[ftmp6], 0x08(%[addr0], %[block]) \n\t"
MMI_SDXC1(%[ftmp5], %[addr0], %[block], 0x00)
MMI_SDXC1(%[ftmp6], %[addr0], %[block], 0x08)
"blez %[addr0], 1b \n\t" "blez %[addr0], 1b \n\t"
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
@@ -410,6 +420,8 @@ void ff_dct_unquantize_mpeg2_intra_mmi(MpegEncContext *s, int16_t *block,
[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]), [ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
[ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]), [ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]),
[tmp0]"=&r"(tmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_ALL64
RESTRICT_ASM_ADDRT
[addr0]"=&r"(addr[0]) [addr0]"=&r"(addr[0])
: [block]"r"((mips_reg)(block+nCoeffs)), : [block]"r"((mips_reg)(block+nCoeffs)),
[quant]"r"((mips_reg)(quant_matrix+nCoeffs)), [quant]"r"((mips_reg)(quant_matrix+nCoeffs)),
@@ -428,15 +440,16 @@ void ff_denoise_dct_mmi(MpegEncContext *s, int16_t *block)
uint16_t *offset = s->dct_offset[intra]; uint16_t *offset = s->dct_offset[intra];
double ftmp[8]; double ftmp[8];
mips_reg addr[1]; mips_reg addr[1];
DECLARE_VAR_ALL64;


s->dct_count[intra]++; s->dct_count[intra]++;


__asm__ volatile( __asm__ volatile(
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"1: \n\t" "1: \n\t"
"ldc1 %[ftmp1], 0x00(%[block]) \n\t"
MMI_LDC1(%[ftmp1], %[block], 0x00)
"xor %[ftmp2], %[ftmp2], %[ftmp2] \n\t" "xor %[ftmp2], %[ftmp2], %[ftmp2] \n\t"
"ldc1 %[ftmp3], 0x08(%[block]) \n\t"
MMI_LDC1(%[ftmp3], %[block], 0x08)
"xor %[ftmp4], %[ftmp4], %[ftmp4] \n\t" "xor %[ftmp4], %[ftmp4], %[ftmp4] \n\t"
"pcmpgth %[ftmp2], %[ftmp2], %[ftmp1] \n\t" "pcmpgth %[ftmp2], %[ftmp2], %[ftmp1] \n\t"
"pcmpgth %[ftmp4], %[ftmp4], %[ftmp3] \n\t" "pcmpgth %[ftmp4], %[ftmp4], %[ftmp3] \n\t"
@@ -444,36 +457,36 @@ void ff_denoise_dct_mmi(MpegEncContext *s, int16_t *block)
"xor %[ftmp3], %[ftmp3], %[ftmp4] \n\t" "xor %[ftmp3], %[ftmp3], %[ftmp4] \n\t"
"psubh %[ftmp1], %[ftmp1], %[ftmp2] \n\t" "psubh %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
"psubh %[ftmp3], %[ftmp3], %[ftmp4] \n\t" "psubh %[ftmp3], %[ftmp3], %[ftmp4] \n\t"
"ldc1 %[ftmp6], 0x00(%[offset]) \n\t"
MMI_LDC1(%[ftmp6], %[offset], 0x00)
"mov.d %[ftmp5], %[ftmp1] \n\t" "mov.d %[ftmp5], %[ftmp1] \n\t"
"psubush %[ftmp1], %[ftmp1], %[ftmp6] \n\t" "psubush %[ftmp1], %[ftmp1], %[ftmp6] \n\t"
"ldc1 %[ftmp6], 0x08(%[offset]) \n\t"
MMI_LDC1(%[ftmp6], %[offset], 0x08)
"mov.d %[ftmp7], %[ftmp3] \n\t" "mov.d %[ftmp7], %[ftmp3] \n\t"
"psubush %[ftmp3], %[ftmp3], %[ftmp6] \n\t" "psubush %[ftmp3], %[ftmp3], %[ftmp6] \n\t"
"xor %[ftmp1], %[ftmp1], %[ftmp2] \n\t" "xor %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
"xor %[ftmp3], %[ftmp3], %[ftmp4] \n\t" "xor %[ftmp3], %[ftmp3], %[ftmp4] \n\t"
"psubh %[ftmp1], %[ftmp1], %[ftmp2] \n\t" "psubh %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
"psubh %[ftmp3], %[ftmp3], %[ftmp4] \n\t" "psubh %[ftmp3], %[ftmp3], %[ftmp4] \n\t"
"sdc1 %[ftmp1], 0x00(%[block]) \n\t"
"sdc1 %[ftmp3], 0x08(%[block]) \n\t"
MMI_SDC1(%[ftmp1], %[block], 0x00)
MMI_SDC1(%[ftmp3], %[block], 0x08)
"mov.d %[ftmp1], %[ftmp5] \n\t" "mov.d %[ftmp1], %[ftmp5] \n\t"
"mov.d %[ftmp3], %[ftmp7] \n\t" "mov.d %[ftmp3], %[ftmp7] \n\t"
"punpcklhw %[ftmp5], %[ftmp5], %[ftmp0] \n\t" "punpcklhw %[ftmp5], %[ftmp5], %[ftmp0] \n\t"
"punpckhhw %[ftmp1], %[ftmp1], %[ftmp0] \n\t" "punpckhhw %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
"punpcklhw %[ftmp7], %[ftmp7], %[ftmp0] \n\t" "punpcklhw %[ftmp7], %[ftmp7], %[ftmp0] \n\t"
"punpckhhw %[ftmp3], %[ftmp3], %[ftmp0] \n\t" "punpckhhw %[ftmp3], %[ftmp3], %[ftmp0] \n\t"
"ldc1 %[ftmp2], 0x00(%[sum]) \n\t"
MMI_LDC1(%[ftmp2], %[sum], 0x00)
"paddw %[ftmp5], %[ftmp5], %[ftmp2] \n\t" "paddw %[ftmp5], %[ftmp5], %[ftmp2] \n\t"
"ldc1 %[ftmp2], 0x08(%[sum]) \n\t"
MMI_LDC1(%[ftmp2], %[sum], 0x08)
"paddw %[ftmp1], %[ftmp1], %[ftmp2] \n\t" "paddw %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
"ldc1 %[ftmp2], 0x10(%[sum]) \n\t"
MMI_LDC1(%[ftmp2], %[sum], 0x10)
"paddw %[ftmp7], %[ftmp7], %[ftmp2] \n\t" "paddw %[ftmp7], %[ftmp7], %[ftmp2] \n\t"
"ldc1 %[ftmp2], 0x18(%[sum]) \n\t"
MMI_LDC1(%[ftmp2], %[sum], 0x18)
"paddw %[ftmp3], %[ftmp3], %[ftmp2] \n\t" "paddw %[ftmp3], %[ftmp3], %[ftmp2] \n\t"
"sdc1 %[ftmp5], 0x00(%[sum]) \n\t"
"sdc1 %[ftmp1], 0x08(%[sum]) \n\t"
"sdc1 %[ftmp7], 0x10(%[sum]) \n\t"
"sdc1 %[ftmp3], 0x18(%[sum]) \n\t"
MMI_SDC1(%[ftmp5], %[sum], 0x00)
MMI_SDC1(%[ftmp1], %[sum], 0x08)
MMI_SDC1(%[ftmp7], %[sum], 0x10)
MMI_SDC1(%[ftmp3], %[sum], 0x18)
PTR_ADDIU "%[block], %[block], 0x10 \n\t" PTR_ADDIU "%[block], %[block], 0x10 \n\t"
PTR_ADDIU "%[sum], %[sum], 0x20 \n\t" PTR_ADDIU "%[sum], %[sum], 0x20 \n\t"
PTR_SUBU "%[addr0], %[block1], %[block] \n\t" PTR_SUBU "%[addr0], %[block1], %[block] \n\t"
@@ -483,6 +496,7 @@ void ff_denoise_dct_mmi(MpegEncContext *s, int16_t *block)
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]), [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]), [ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
RESTRICT_ASM_ALL64
[addr0]"=&r"(addr[0]), [addr0]"=&r"(addr[0]),
[block]"+&r"(block), [sum]"+&r"(sum), [block]"+&r"(block), [sum]"+&r"(sum),
[offset]"+&r"(offset) [offset]"+&r"(offset)


+ 62
- 25
libavcodec/mips/pixblockdsp_mmi.c View File

@@ -23,34 +23,73 @@


#include "pixblockdsp_mips.h" #include "pixblockdsp_mips.h"
#include "libavutil/mips/asmdefs.h" #include "libavutil/mips/asmdefs.h"
#include "libavutil/mips/mmiutils.h"


void ff_get_pixels_8_mmi(int16_t *av_restrict block, const uint8_t *pixels, void ff_get_pixels_8_mmi(int16_t *av_restrict block, const uint8_t *pixels,
ptrdiff_t line_size) ptrdiff_t line_size)
{ {
double ftmp[6];
mips_reg tmp[2];
double ftmp[7];
DECLARE_VAR_ALL64;
DECLARE_VAR_ADDRT;


__asm__ volatile ( __asm__ volatile (
"li %[tmp1], 0x08 \n\t"
"move %[tmp0], $0 \n\t"
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t" "xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"1: \n\t"
"gsldlc1 %[ftmp1], 0x07(%[pixels]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[pixels]) \n\t"
"punpcklbh %[ftmp2], %[ftmp1], %[ftmp0] \n\t"
"punpckhbh %[ftmp5], %[ftmp1], %[ftmp0] \n\t"
"gssdxc1 %[ftmp2], 0x00(%[block], %[tmp0]) \n\t"
"gssdxc1 %[ftmp5], 0x08(%[block], %[tmp0]) \n\t"
PTR_ADDI "%[tmp1], %[tmp1], -0x01 \n\t"
PTR_ADDIU "%[tmp0], %[tmp0], 0x10 \n\t"
PTR_ADDU "%[pixels], %[pixels], %[line_size] \n\t"
"bnez %[tmp1], 1b \n\t"

MMI_LDC1(%[ftmp1], %[pixels], 0x00)
MMI_LDXC1(%[ftmp2], %[pixels], %[line_size], 0x00)
"punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
"punpckhbh %[ftmp4], %[ftmp1], %[ftmp0] \n\t"
"punpcklbh %[ftmp5], %[ftmp2], %[ftmp0] \n\t"
"punpckhbh %[ftmp6], %[ftmp2], %[ftmp0] \n\t"
MMI_SDC1(%[ftmp3], %[block], 0x00)
MMI_SDC1(%[ftmp4], %[block], 0x08)
MMI_SDC1(%[ftmp5], %[block], 0x10)
MMI_SDC1(%[ftmp6], %[block], 0x18)
PTR_ADDU "%[pixels], %[pixels], %[line_size_x2] \n\t"

MMI_LDC1(%[ftmp1], %[pixels], 0x00)
MMI_LDXC1(%[ftmp2], %[pixels], %[line_size], 0x00)
"punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
"punpckhbh %[ftmp4], %[ftmp1], %[ftmp0] \n\t"
"punpcklbh %[ftmp5], %[ftmp2], %[ftmp0] \n\t"
"punpckhbh %[ftmp6], %[ftmp2], %[ftmp0] \n\t"
MMI_SDC1(%[ftmp3], %[block], 0x20)
MMI_SDC1(%[ftmp4], %[block], 0x28)
MMI_SDC1(%[ftmp5], %[block], 0x30)
MMI_SDC1(%[ftmp6], %[block], 0x38)
PTR_ADDU "%[pixels], %[pixels], %[line_size_x2] \n\t"

MMI_LDC1(%[ftmp1], %[pixels], 0x00)
MMI_LDXC1(%[ftmp2], %[pixels], %[line_size], 0x00)
"punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
"punpckhbh %[ftmp4], %[ftmp1], %[ftmp0] \n\t"
"punpcklbh %[ftmp5], %[ftmp2], %[ftmp0] \n\t"
"punpckhbh %[ftmp6], %[ftmp2], %[ftmp0] \n\t"
MMI_SDC1(%[ftmp3], %[block], 0x40)
MMI_SDC1(%[ftmp4], %[block], 0x48)
MMI_SDC1(%[ftmp5], %[block], 0x50)
MMI_SDC1(%[ftmp6], %[block], 0x58)
PTR_ADDU "%[pixels], %[pixels], %[line_size_x2] \n\t"

MMI_LDC1(%[ftmp1], %[pixels], 0x00)
MMI_LDXC1(%[ftmp2], %[pixels], %[line_size], 0x00)
"punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
"punpckhbh %[ftmp4], %[ftmp1], %[ftmp0] \n\t"
"punpcklbh %[ftmp5], %[ftmp2], %[ftmp0] \n\t"
"punpckhbh %[ftmp6], %[ftmp2], %[ftmp0] \n\t"
MMI_SDC1(%[ftmp3], %[block], 0x60)
MMI_SDC1(%[ftmp4], %[block], 0x68)
MMI_SDC1(%[ftmp5], %[block], 0x70)
MMI_SDC1(%[ftmp6], %[block], 0x78)
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]), : [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]), [ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
[tmp0]"=&r"(tmp[0]), [tmp1]"=&r"(tmp[1]),
[ftmp6]"=&f"(ftmp[6]),
RESTRICT_ASM_ALL64
RESTRICT_ASM_ADDRT
[pixels]"+&r"(pixels) [pixels]"+&r"(pixels)
: [block]"r"((mips_reg)block), [line_size]"r"((mips_reg)line_size)
: [block]"r"((mips_reg)block), [line_size]"r"((mips_reg)line_size),
[line_size_x2]"r"((mips_reg)(line_size<<1))
: "memory" : "memory"
); );
} }
@@ -60,16 +99,15 @@ void ff_diff_pixels_mmi(int16_t *av_restrict block, const uint8_t *src1,
{ {
double ftmp[5]; double ftmp[5];
mips_reg tmp[1]; mips_reg tmp[1];
DECLARE_VAR_ALL64;


__asm__ volatile ( __asm__ volatile (
"li %[tmp0], 0x08 \n\t" "li %[tmp0], 0x08 \n\t"
"xor %[ftmp4], %[ftmp4], %[ftmp4] \n\t" "xor %[ftmp4], %[ftmp4], %[ftmp4] \n\t"
"1: \n\t" "1: \n\t"
"gsldlc1 %[ftmp0], 0x07(%[src1]) \n\t"
"gsldrc1 %[ftmp0], 0x00(%[src1]) \n\t"
MMI_LDC1(%[ftmp0], %[src1], 0x00)
"or %[ftmp1], %[ftmp0], %[ftmp0] \n\t" "or %[ftmp1], %[ftmp0], %[ftmp0] \n\t"
"gsldlc1 %[ftmp2], 0x07(%[src2]) \n\t"
"gsldrc1 %[ftmp2], 0x00(%[src2]) \n\t"
MMI_LDC1(%[ftmp2], %[src2], 0x00)
"or %[ftmp3], %[ftmp2], %[ftmp2] \n\t" "or %[ftmp3], %[ftmp2], %[ftmp2] \n\t"
"punpcklbh %[ftmp0], %[ftmp0], %[ftmp4] \n\t" "punpcklbh %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
"punpckhbh %[ftmp1], %[ftmp1], %[ftmp4] \n\t" "punpckhbh %[ftmp1], %[ftmp1], %[ftmp4] \n\t"
@@ -77,10 +115,8 @@ void ff_diff_pixels_mmi(int16_t *av_restrict block, const uint8_t *src1,
"punpckhbh %[ftmp3], %[ftmp3], %[ftmp4] \n\t" "punpckhbh %[ftmp3], %[ftmp3], %[ftmp4] \n\t"
"psubh %[ftmp0], %[ftmp0], %[ftmp2] \n\t" "psubh %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
"psubh %[ftmp1], %[ftmp1], %[ftmp3] \n\t" "psubh %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
"gssdlc1 %[ftmp0], 0x07(%[block]) \n\t"
"gssdrc1 %[ftmp0], 0x00(%[block]) \n\t"
"gssdlc1 %[ftmp1], 0x0f(%[block]) \n\t"
"gssdrc1 %[ftmp1], 0x08(%[block]) \n\t"
MMI_SDC1(%[ftmp0], %[block], 0x00)
MMI_SDC1(%[ftmp1], %[block], 0x08)
PTR_ADDI "%[tmp0], %[tmp0], -0x01 \n\t" PTR_ADDI "%[tmp0], %[tmp0], -0x01 \n\t"
PTR_ADDIU "%[block], %[block], 0x10 \n\t" PTR_ADDIU "%[block], %[block], 0x10 \n\t"
PTR_ADDU "%[src1], %[src1], %[stride] \n\t" PTR_ADDU "%[src1], %[src1], %[stride] \n\t"
@@ -90,6 +126,7 @@ void ff_diff_pixels_mmi(int16_t *av_restrict block, const uint8_t *src1,
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]), [ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
[ftmp4]"=&f"(ftmp[4]), [ftmp4]"=&f"(ftmp[4]),
[tmp0]"=&r"(tmp[0]), [tmp0]"=&r"(tmp[0]),
RESTRICT_ASM_ALL64
[block]"+&r"(block), [src1]"+&r"(src1), [block]"+&r"(block), [src1]"+&r"(src1),
[src2]"+&r"(src2) [src2]"+&r"(src2)
: [stride]"r"((mips_reg)stride) : [stride]"r"((mips_reg)stride)


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