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  1. ///////////////////////////////////////////////////
  2. //
  3. // Logic Gates VCV Module
  4. //
  5. // Strum 2017
  6. //
  7. ///////////////////////////////////////////////////
  8. #include "mental.hpp"
  9. namespace rack_plugin_mental {
  10. struct MentalLogic : Module {
  11. enum ParamIds {
  12. NUM_PARAMS
  13. };
  14. enum InputIds {
  15. INPUT_A_1,
  16. INPUT_B_1,
  17. INPUT_A_2,
  18. INPUT_B_2,
  19. INPUT_INV_1,
  20. INPUT_INV_2,
  21. INPUT_A_3,
  22. INPUT_B_3,
  23. INPUT_C_3,
  24. INPUT_D_3,
  25. INPUT_E_3,
  26. NUM_INPUTS
  27. };
  28. enum OutputIds {
  29. OUTPUT_AND_1,
  30. OUTPUT_OR_1,
  31. OUTPUT_AND_2,
  32. OUTPUT_OR_2,
  33. OUTPUT_INV_1,
  34. OUTPUT_INV_2,
  35. OUTPUT_OR_3,
  36. NUM_OUTPUTS
  37. };
  38. enum LightIds {
  39. AND_LED_1,
  40. OR_LED_1,
  41. AND_LED_2,
  42. OR_LED_2,
  43. INV_LED_1,
  44. INV_LED_2,
  45. OR_LED_3,
  46. NUM_LIGHTS
  47. };
  48. MentalLogic() : Module(NUM_PARAMS, NUM_INPUTS, NUM_OUTPUTS, NUM_LIGHTS) {}
  49. void step() override;
  50. };
  51. void MentalLogic::step()
  52. {
  53. float signal_in_A1 = inputs[INPUT_A_1].value;
  54. float signal_in_B1 = inputs[INPUT_B_1].value;
  55. float signal_in_A2 = inputs[INPUT_A_2].value;
  56. float signal_in_B2 = inputs[INPUT_B_2].value;
  57. float inv_1_input = inputs[INPUT_INV_1].value;
  58. float inv_2_input = inputs[INPUT_INV_2].value;
  59. float or_3_A_input = inputs[INPUT_A_3].value;
  60. float or_3_B_input = inputs[INPUT_B_3].value;
  61. float or_3_C_input = inputs[INPUT_C_3].value;
  62. float or_3_D_input = inputs[INPUT_D_3].value;
  63. float or_3_E_input = inputs[INPUT_E_3].value;
  64. if (inv_1_input > 0.0)
  65. {
  66. outputs[OUTPUT_INV_1].value = 0.0;
  67. lights[INV_LED_1].value = 0.0;
  68. }
  69. else
  70. {
  71. outputs[OUTPUT_INV_1].value = 10.0;
  72. lights[INV_LED_1].value = 1.0;
  73. }
  74. if (inv_2_input > 0.0)
  75. {
  76. outputs[OUTPUT_INV_2].value = 0.0;
  77. lights[INV_LED_2].value = 0.0;
  78. }
  79. else
  80. {
  81. outputs[OUTPUT_INV_2].value = 10.0;
  82. lights[INV_LED_2].value = 1.0;
  83. }
  84. //////////////////////////
  85. if (signal_in_A1 > 0.0 && signal_in_B1 > 0.0 )
  86. {
  87. outputs[OUTPUT_AND_1].value = 10.0;
  88. lights[AND_LED_1].value = 1.0;
  89. }
  90. else
  91. {
  92. outputs[OUTPUT_AND_1].value = 0.0;
  93. lights[AND_LED_1].value = 0.0;
  94. }
  95. if (signal_in_A1 > 0.0 || signal_in_B1 > 0.0 )
  96. {
  97. outputs[OUTPUT_OR_1].value = 10.0;
  98. lights[OR_LED_1].value = 1.0;
  99. }
  100. else
  101. {
  102. outputs[OUTPUT_OR_1].value = 0.0;
  103. lights[OR_LED_1].value = 0.0;
  104. }
  105. //////////////////////////////////////
  106. if (signal_in_A2 > 0.0 && signal_in_B2 > 0.0 )
  107. {
  108. outputs[OUTPUT_AND_2].value = 10.0;
  109. lights[AND_LED_2].value = 1.0;
  110. }
  111. else
  112. {
  113. outputs[OUTPUT_AND_2].value = 0.0;
  114. lights[AND_LED_2].value = 0.0;
  115. }
  116. if (signal_in_A2 > 0.0 || signal_in_B2 > 0.0 )
  117. {
  118. outputs[OUTPUT_OR_2].value = 10.0;
  119. lights[OR_LED_2].value = 1.0;
  120. }
  121. else
  122. {
  123. outputs[OUTPUT_OR_2].value = 0.0;
  124. lights[OR_LED_2].value = 0.0;
  125. }
  126. //////////////// Big or
  127. if ( or_3_A_input > 0.0 || or_3_B_input > 0.0 || or_3_C_input > 0.0 || or_3_D_input > 0.0 || or_3_E_input > 0.0 )
  128. {
  129. outputs[OUTPUT_OR_3].value = 10.0;
  130. lights[OR_LED_3].value = 1.0;
  131. }
  132. else
  133. {
  134. outputs[OUTPUT_OR_3].value = 0.0;
  135. lights[OR_LED_3].value = 0.0;
  136. }
  137. }
  138. /////////////////////////
  139. struct MentalLogicWidget : ModuleWidget {
  140. MentalLogicWidget(MentalLogic *module);
  141. };
  142. MentalLogicWidget::MentalLogicWidget(MentalLogic *module) : ModuleWidget(module)
  143. {
  144. setPanel(SVG::load(assetPlugin(plugin, "res/MentalLogic.svg")));
  145. int input_column = 3;
  146. int output_column = 28;
  147. int led_column = 58;
  148. int first_row = 25;
  149. int row_spacing = 25;
  150. int vert_offset = 60;
  151. addInput(Port::create<GateInPort>(Vec(input_column, first_row), Port::INPUT, module, MentalLogic::INPUT_A_1));
  152. addInput(Port::create<GateInPort>(Vec(input_column, first_row+row_spacing), Port::INPUT, module, MentalLogic::INPUT_B_1));
  153. addOutput(Port::create<GateOutPort>(Vec(output_column, first_row), Port::OUTPUT, module, MentalLogic::OUTPUT_AND_1));
  154. addOutput(Port::create<GateOutPort>(Vec(output_column, first_row+row_spacing), Port::OUTPUT, module, MentalLogic::OUTPUT_OR_1));
  155. addChild(ModuleLightWidget::create<MedLight<BlueLED>>(Vec(led_column, first_row + 8), module, MentalLogic::AND_LED_1));
  156. addChild(ModuleLightWidget::create<MedLight<BlueLED>>(Vec(led_column, first_row+row_spacing + 8), module, MentalLogic::OR_LED_1));
  157. ////////////////////////////
  158. addInput(Port::create<GateInPort>(Vec(input_column, vert_offset + first_row), Port::INPUT, module, MentalLogic::INPUT_A_2));
  159. addInput(Port::create<GateInPort>(Vec(input_column, vert_offset + first_row + row_spacing), Port::INPUT, module, MentalLogic::INPUT_B_2));
  160. addOutput(Port::create<GateOutPort>(Vec(output_column, vert_offset + first_row), Port::OUTPUT, module, MentalLogic::OUTPUT_AND_2));
  161. addOutput(Port::create<GateOutPort>(Vec(output_column, vert_offset + first_row + row_spacing), Port::OUTPUT, module, MentalLogic::OUTPUT_OR_2));
  162. addChild(ModuleLightWidget::create<MedLight<BlueLED>>(Vec(led_column, vert_offset + first_row + 8), module, MentalLogic::AND_LED_2));
  163. addChild(ModuleLightWidget::create<MedLight<BlueLED>>(Vec(led_column, vert_offset +first_row + row_spacing + 8), module, MentalLogic::OR_LED_2));
  164. ///// Inverters
  165. addInput(Port::create<GateInPort>(Vec(input_column, vert_offset * 2 + first_row), Port::INPUT, module, MentalLogic::INPUT_INV_1));
  166. addInput(Port::create<GateInPort>(Vec(input_column, vert_offset * 2 + first_row + row_spacing), Port::INPUT, module, MentalLogic::INPUT_INV_2));
  167. addOutput(Port::create<GateOutPort>(Vec(output_column, vert_offset * 2 + first_row), Port::OUTPUT, module, MentalLogic::OUTPUT_INV_1));
  168. addOutput(Port::create<GateOutPort>(Vec(output_column, vert_offset * 2 + first_row + row_spacing), Port::OUTPUT, module, MentalLogic::OUTPUT_INV_2));
  169. addChild(ModuleLightWidget::create<MedLight<BlueLED>>(Vec(led_column, vert_offset * 2 + first_row + 8), module, MentalLogic::INV_LED_1));
  170. addChild(ModuleLightWidget::create<MedLight<BlueLED>>(Vec(led_column, vert_offset * 2 + first_row + row_spacing + 8), module, MentalLogic::INV_LED_2));
  171. ////// Big or
  172. addInput(Port::create<GateInPort>(Vec(input_column, vert_offset + 150), Port::INPUT, module, MentalLogic::INPUT_A_3));
  173. addInput(Port::create<GateInPort>(Vec(input_column, vert_offset + 175), Port::INPUT, module, MentalLogic::INPUT_B_3));
  174. addInput(Port::create<GateInPort>(Vec(input_column, vert_offset + 200), Port::INPUT, module, MentalLogic::INPUT_C_3));
  175. addInput(Port::create<GateInPort>(Vec(input_column, vert_offset + 225), Port::INPUT, module, MentalLogic::INPUT_D_3));
  176. addInput(Port::create<GateInPort>(Vec(input_column, vert_offset + 250), Port::INPUT, module, MentalLogic::INPUT_E_3));
  177. addOutput(Port::create<GateOutPort>(Vec(output_column, vert_offset + 150), Port::OUTPUT, module, MentalLogic::OUTPUT_OR_3));
  178. addChild(ModuleLightWidget::create<MedLight<BlueLED>>(Vec(led_column, vert_offset + 158), module, MentalLogic::OR_LED_3));
  179. }
  180. } // namespace rack_plugin_mental
  181. using namespace rack_plugin_mental;
  182. RACK_PLUGIN_MODEL_INIT(mental, MentalLogic) {
  183. Model *modelMentalLogic = Model::create<MentalLogic, MentalLogicWidget>("mental", "MentalLogic", "Logic Gates", UTILITY_TAG);
  184. return modelMentalLogic;
  185. }